From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932342AbcFLHjN (ORCPT ); Sun, 12 Jun 2016 03:39:13 -0400 Received: from lucky1.263xmail.com ([211.157.147.135]:57773 "EHLO lucky1.263xmail.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932081AbcFLHjL (ORCPT ); Sun, 12 Jun 2016 03:39:11 -0400 X-263anti-spam: KSV:0; X-MAIL-GRAY: 1 X-MAIL-DELIVERY: 0 X-KSVirus-check: 0 X-ABS-CHECKED: 4 X-ADDR-CHECKED: 0 X-RL-SENDER: shawn.lin@rock-chips.com X-FST-TO: kishon@ti.com X-SENDER-IP: 58.22.7.114 X-LOGIN-NAME: shawn.lin@rock-chips.com X-UNIQUE-TAG: <18b7e06c1a645f2554087806c23166ec> X-ATTACHMENT-NUM: 0 X-DNS-TYPE: 0 Subject: Re: [PATCH 1/2] Documentation: bindings: add dt documentation for Rockchip PCIe PHY To: =?UTF-8?Q?Heiko_St=c3=bcbner?= , Rob Herring References: <1465370708-23619-1-git-send-email-shawn.lin@rock-chips.com> <20160608202900.GA25662@rob-hp-laptop> <1524911.R4OXTTYFIK@diego> Cc: shawn.lin@rock-chips.com, devicetree@vger.kernel.org, Wenrui Li , Doug Anderson , linux-kernel@vger.kernel.org, linux-rockchip@lists.infradead.org, Kishon Vijay Abraham I From: Shawn Lin Message-ID: Date: Sun, 12 Jun 2016 15:38:52 +0800 User-Agent: Mozilla/5.0 (Windows NT 6.3; WOW64; rv:45.0) Gecko/20100101 Thunderbird/45.1.1 MIME-Version: 1.0 In-Reply-To: <1524911.R4OXTTYFIK@diego> Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 2016/6/9 4:40, Heiko Stübner wrote: > Am Mittwoch, 8. Juni 2016, 15:29:00 schrieb Rob Herring: >> gOn Wed, Jun 08, 2016 at 03:25:08PM +0800, Shawn Lin wrote: >>> This patch adds a binding that describes the Rockchip PCIe PHY >>> found on Rockchip SoCs PCIe interface. >>> >>> Signed-off-by: Shawn Lin >>> --- >>> >>> .../devicetree/bindings/phy/rockchip-pcie-phy.txt | 22 >>> ++++++++++++++++++++++ 1 file changed, 22 insertions(+) >>> create mode 100644 >>> Documentation/devicetree/bindings/phy/rockchip-pcie-phy.txt> >>> diff --git a/Documentation/devicetree/bindings/phy/rockchip-pcie-phy.txt >>> b/Documentation/devicetree/bindings/phy/rockchip-pcie-phy.txt new file >>> mode 100644 >>> index 0000000..ba8c406 >>> --- /dev/null >>> +++ b/Documentation/devicetree/bindings/phy/rockchip-pcie-phy.txt >>> @@ -0,0 +1,22 @@ >>> +Rockchip PCIE PHY >>> +----------------------- >>> + >>> +Required properties: >>> + - compatible: rockchip,rk3399-pcie-phy >>> + - #phy-cells: must be 0 >>> + >>> +Example: >>> + >>> +grf: syscon@ff770000 { >>> + compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd"; >>> + #address-cells = <1>; >>> + #size-cells = <1>; >>> + >>> + ... >>> + >>> + pcie_phy: phy@e220 { >> >> unit-address needs a reg property or drop the unit address. I'd do the >> former if there's a register range you can describe here. > > Hmm, I think I'd suggest going the other way - call the node pcie-phy . pcie phy does not cantain a reg range, so I will drop the unit-address. > > While the General Register Files do contain some specific address ranges (like > for the emmc phy, or some performance monitor things), the register at 0xe220 > is a shared register (GRF_SOC_CON8), containing both i2s and pcie setting > bits. yes, we only need two bits: test_addr(for pcie phy's internal configure address) and test_i(corresponding value for the address given) whthin GRF_SOC_CON8 to W/R the phy. > > Specifying register ranges suggests some form of exclusivity to me - which is > just great for things like the emmc phy that has an actual range, but for a > device being controlled from some shared register. > > > Heiko > > > _______________________________________________ > Linux-rockchip mailing list > Linux-rockchip@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-rockchip > -- Best Regards Shawn Lin