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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b9084e4bf43sm528962766b.42.2026.02.25.06.18.07 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 25 Feb 2026 06:18:09 -0800 (PST) Message-ID: Date: Wed, 25 Feb 2026 15:18:06 +0100 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3] arm64: dts: qcom: sm8750: Add camera clock controller To: Taniya Das , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Ajit Pandey , Imran Shaik , Jagadeesh Kona , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Abel Vesa References: <20260225-sm8750_camcc_dt-v3-1-a19d3173a160@oss.qualcomm.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: <20260225-sm8750_camcc_dt-v3-1-a19d3173a160@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMjI1MDEzNiBTYWx0ZWRfX1mBqg3RQkkaV yNkTHZrgJqQC980GuqeUv/s8UyjWZIOEYAOa4YHT6Np4Mi/7xvhN9HSSf4pF9GpsM2YvRlLL7Ui tDdYca1YM1gZwv7VBzBVSkohNhosGv/B6WO3Svu85C/PG+9WUwtafXfEvOgrFdxGui5SNtX/c3X Zl3ezy1qN2gnsFRD0Q02b+cB5DC1g8/lEVaJ7/EA+MYu6IZDATDn5TRUdaVqys/E9BPbjQVfwJo JooA1HaMo/12FgnnsbQnLVfdrz+3igrqKwN3/93FSVqjMr8+qcqD84KHMvqITuFLMPC5fvG8KFh LGRuz/6MYFq06L1Sy2FXcHLRRQx/bqTi02LDWT92P1lZz4+TH6fRnhgLZ1Rt5x3PNvxaZl0xkSC KxO4XTHoQoHtJTsBgHG6DJiZ2dKpW0PyZiJ2xpGdaoQn/M0XGrxGzxjoA4ifpLmQ0Vqunrm3U6I c/1kx84t+9T3mXpg9Hw== X-Proofpoint-GUID: b2P8HpaF7VLRzGJ4weNMwFJrkTwQsk2V X-Proofpoint-ORIG-GUID: b2P8HpaF7VLRzGJ4weNMwFJrkTwQsk2V X-Authority-Analysis: v=2.4 cv=NeDrFmD4 c=1 sm=1 tr=0 ts=699f04a5 cx=c_pps a=50t2pK5VMbmlHzFWWp8p/g==:117 a=FpWmc02/iXfjRdCD7H54yg==:17 a=IkcTkHD0fZMA:10 a=HzLeVaNsDn8A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=DJpcGTmdVt4CTyJn9g5Z:22 a=EUspDBNiAAAA:8 a=ZF7kzkCWYRGncH6IDUMA:9 a=QEXdDO2ut3YA:10 a=IoWCM6iH3mJn3m4BftBB:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-02-25_01,2026-02-25_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 bulkscore=0 adultscore=0 spamscore=0 priorityscore=1501 suspectscore=0 lowpriorityscore=0 phishscore=0 malwarescore=0 clxscore=1015 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2602130000 definitions=main-2602250136 On 2/25/26 11:12 AM, Taniya Das wrote: > The camera clock controller is split into cambistmclk and camcc. The > cambist clock controller handles the mclks and the rest of the clocks of > camera are part of the camcc clock controller. > Add the camcc clock controller device node for SM8750 SoC. > > Reviewed-by: Abel Vesa > Signed-off-by: Taniya Das > --- [...] > + cambistmclkcc: clock-controller@1760000 { > + compatible = "qcom,sm8750-cambistmclkcc"; > + reg = <0x0 0x1760000 0x0 0x6000>; > + clocks = <&gcc GCC_CAM_BIST_MCLK_AHB_CLK> , Stray space before the comma > + <&bi_tcxo_div2>, > + <&bi_tcxo_ao_div2>, > + <&sleep_clk>; > + power-domains = <&rpmhpd RPMHPD_MMCX>, I find it difficult to believe, but the computer tells me CAM_BIST_MCLK_CC is powered from *CX*, notably *not MMCX*, could you please double-check that as well? FWIW, the other (MXA) rail seems to be OK Konrad