From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 51C7A3033C8 for ; Mon, 16 Feb 2026 10:59:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1771239555; cv=none; b=Vi0cV8toUkszcD5a+XAaRL3cfuby77STYUp3GQOnPRJjx2BO6mEm52gUCV0Dkl1O5O8uno4GwIRbMAwPEOxiHTLWl3OaoLry2++sRMZNe7v7aS5GX422KUOwAJoSIMqBs56Pjl8x0Cu5j/26zULWF2n+MewLb+ZXb39Fve773i8= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1771239555; c=relaxed/simple; bh=bWB4Ho1jWu8bS4yZsWww4NOQJBpLktuWCIEjSR5NJKs=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=TOKJ53FdUIRws1vP8TmYjraUQgxIbCRn3Or2QH/r7X5rwAqkEGVDG/q6W857WsTPfRwUrgIFWdvqv3eJTD6UaDKep2/P4Hfva6MEdmevgbNh2DsjMxuwvq0pVrdSUa7eY9hJfmNeRMxE089VjElavBpBgpFhezF+mWwESwPgyMQ= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 666D11570; Mon, 16 Feb 2026 02:59:06 -0800 (PST) Received: from [10.164.19.71] (unknown [10.164.19.71]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 640983F632; Mon, 16 Feb 2026 02:59:10 -0800 (PST) Message-ID: Date: Mon, 16 Feb 2026 16:29:07 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH] arm64: remove HAVE_CMPXCHG_LOCAL To: Jisheng Zhang , Catalin Marinas , Will Deacon , Dennis Zhou , Tejun Heo , Christoph Lameter Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mm@kvack.org References: <20260215033944.16374-1-jszhang@kernel.org> Content-Language: en-US From: Dev Jain In-Reply-To: <20260215033944.16374-1-jszhang@kernel.org> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit On 15/02/26 9:09 am, Jisheng Zhang wrote: > It turns out the generic disable/enable irq this_cpu_cmpxchg > implementation is faster than LL/SC or lse implementation. Remove > HAVE_CMPXCHG_LOCAL for better performance on arm64. > > Tested on Quad 1.9GHZ CA55 platform: > average mod_node_page_state() cost decreases from 167ns to 103ns > the spawn (30 duration) benchmark in unixbench is improved > from 147494 lps to 150561 lps, improved by 2.1% > > Tested on Quad 2.1GHZ CA73 platform: > average mod_node_page_state() cost decreases from 113ns to 85ns > the spawn (30 duration) benchmark in unixbench is improved > from 209844 lps to 212581 lps, improved by 1.3% > > Signed-off-by: Jisheng Zhang > --- Thanks. This concurs with my investigation on [1]. The problem isn't really LL/SC/LSE but preempt_disable()/enable() in this_cpu_* [1, 2]. I think you should only remove the selection of the config, but keep the code? We may want to switch this on again if the real issue gets solved. [1] https://lore.kernel.org/all/5a6782f3-d758-4d9c-975b-5ae4b5d80d4e@arm.com/ [2] https://lore.kernel.org/all/CAHbLzkpcN-T8MH6=W3jCxcFj1gVZp8fRqe231yzZT-rV_E_org@mail.gmail.com/ > arch/arm64/Kconfig | 1 - > arch/arm64/include/asm/percpu.h | 24 ------------------------ > 2 files changed, 25 deletions(-) > > diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig > index 38dba5f7e4d2..5e7e2e65d5a5 100644 > --- a/arch/arm64/Kconfig > +++ b/arch/arm64/Kconfig > @@ -205,7 +205,6 @@ config ARM64 > select HAVE_EBPF_JIT > select HAVE_C_RECORDMCOUNT > select HAVE_CMPXCHG_DOUBLE > - select HAVE_CMPXCHG_LOCAL > select HAVE_CONTEXT_TRACKING_USER > select HAVE_DEBUG_KMEMLEAK > select HAVE_DMA_CONTIGUOUS > diff --git a/arch/arm64/include/asm/percpu.h b/arch/arm64/include/asm/percpu.h > index b57b2bb00967..70ffe566cb4b 100644 > --- a/arch/arm64/include/asm/percpu.h > +++ b/arch/arm64/include/asm/percpu.h > @@ -232,30 +232,6 @@ PERCPU_RET_OP(add, add, ldadd) > #define this_cpu_xchg_8(pcp, val) \ > _pcp_protect_return(xchg_relaxed, pcp, val) > > -#define this_cpu_cmpxchg_1(pcp, o, n) \ > - _pcp_protect_return(cmpxchg_relaxed, pcp, o, n) > -#define this_cpu_cmpxchg_2(pcp, o, n) \ > - _pcp_protect_return(cmpxchg_relaxed, pcp, o, n) > -#define this_cpu_cmpxchg_4(pcp, o, n) \ > - _pcp_protect_return(cmpxchg_relaxed, pcp, o, n) > -#define this_cpu_cmpxchg_8(pcp, o, n) \ > - _pcp_protect_return(cmpxchg_relaxed, pcp, o, n) > - > -#define this_cpu_cmpxchg64(pcp, o, n) this_cpu_cmpxchg_8(pcp, o, n) > - > -#define this_cpu_cmpxchg128(pcp, o, n) \ > -({ \ > - typedef typeof(pcp) pcp_op_T__; \ > - u128 old__, new__, ret__; \ > - pcp_op_T__ *ptr__; \ > - old__ = o; \ > - new__ = n; \ > - preempt_disable_notrace(); \ > - ptr__ = raw_cpu_ptr(&(pcp)); \ > - ret__ = cmpxchg128_local((void *)ptr__, old__, new__); \ > - preempt_enable_notrace(); \ > - ret__; \ > -}) > > #ifdef __KVM_NVHE_HYPERVISOR__ > extern unsigned long __hyp_per_cpu_offset(unsigned int cpu);