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> }; > > + gxclkctl: clock-controller@3d64000 { > + compatible = "qcom,glymur-gxclkctl"; > + reg = <0x0 0x03d64000 0x0 0x6000>; > + > + power-domains = <&rpmhpd RPMHPD_GFX>, > + <&rpmhpd RPMHPD_GMXC>, > + <&gpucc GPU_CC_CX_GDSC>; > + > + #power-domain-cells = <1>; > + }; > + > + gpucc: clock-controller@3d90000 { > + compatible = "qcom,glymur-gpucc"; > + reg = <0x0 0x03d90000 0x0 0x9800>; > + clocks = <&rpmhcc RPMH_CXO_CLK>, > + <&gcc GCC_GPU_GPLL0_CLK_SRC>, > + <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; > + Missing power-domains and required-opp properties here. -Akhil > + #clock-cells = <1>; > + #reset-cells = <1>; > + #power-domain-cells = <1>; > + }; > + > ipcc: mailbox@3e04000 { > compatible = "qcom,glymur-ipcc", "qcom,ipcc"; > reg = <0x0 0x03e04000 0x0 0x1000>; > @@ -3367,6 +3393,22 @@ lpass_ag_noc: interconnect@7e40000 { > #interconnect-cells = <2>; > }; > > + videocc: clock-controller@aaf0000 { > + compatible = "qcom,glymur-videocc"; > + reg = <0x0 0x0aaf0000 0x0 0x10000>; > + clocks = <&rpmhcc RPMH_CXO_CLK>, > + <&rpmhcc RPMH_CXO_CLK_A>; > + > + power-domains = <&rpmhpd RPMHPD_MMCX>, > + <&rpmhpd RPMHPD_MXC>; > + required-opps = <&rpmhpd_opp_low_svs>, > + <&rpmhpd_opp_low_svs>; > + > + #clock-cells = <1>; > + #reset-cells = <1>; > + #power-domain-cells = <1>; > + }; > + > dispcc: clock-controller@af00000 { > compatible = "qcom,glymur-dispcc"; > reg = <0x0 0x0af00000 0x0 0x20000>; >