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([2401:4900:889d:214b:d73:b128:21b8:6188]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-c5edf354b24sm1338540a12.28.2026.01.16.00.13.24 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 16 Jan 2026 00:13:31 -0800 (PST) Message-ID: Date: Fri, 16 Jan 2026 13:43:21 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v6 0/8] Support for Adreno 612 GPU - Respin To: rob.clark@oss.qualcomm.com Cc: Sean Paul , Konrad Dybcio , Dmitry Baryshkov , Abhinav Kumar , Marijn Suijten , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Jessica Zhang , Gaurav Kohli , Dan Carpenter , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Jie Zhang , Dmitry Baryshkov , Krzysztof Kozlowski , Krzysztof Kozlowski , Qingqing Zhou , Konrad Dybcio , Jie Zhang References: <20251231-qcs615-spin-2-v6-0-da87debf6883@oss.qualcomm.com> Content-Language: en-US From: Akhil P Oommen In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMTE2MDA2MCBTYWx0ZWRfX2D5905qgQClo /XeQxVC5gKM0hjZzrW7N2aLr4vGg/JBp96XFZvlaasOBtMLMg1AJIw5e43sugQe449hmuYplpCL gBKCHlKrhTT21p7pNi8yvqadC40wRHaqw0anGs4x29WSiHQXdRvICt9fnwMZqW+m86u93uiJoNe PBco34DouM4uunQc7/tt2TUEbSS8+v5xZbWT3h8nqRj67eNENPraA9EOPdG/RIvaXf30P+oO7LX o+m3Wv5xXz8PZ5tiK8VDzex0ZZIPokNdG94Xob92XmxjcP9uIeLlnK0IuZkv2frNLKNXA+TO1UX qPflferS4f0e2gH3r9WFrCknuN/mK05vzqAgXjcaNNpZf7yDyvNRskj+6LYXtxOrP/1AoftpCvV FOSWgMRkabnopEvguoZoQzJw5ktNN9clw2732MI6AXIQ7Io+Hv4AbShfwtOUVhi517W031aEiCL THwpvz0UFqbpJoBiFHA== X-Proofpoint-ORIG-GUID: oYOYRfKm6AQpJGHGmslVXIy23RqMHKBF X-Proofpoint-GUID: oYOYRfKm6AQpJGHGmslVXIy23RqMHKBF X-Authority-Analysis: v=2.4 cv=TsTrRTXh c=1 sm=1 tr=0 ts=6969f32d cx=c_pps a=Qgeoaf8Lrialg5Z894R3/Q==:117 a=xqWC_Br6kY4A:10 a=IkcTkHD0fZMA:10 a=vUbySO9Y5rIA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=VwQbUJbxAAAA:8 a=COk6AnOGAAAA:8 a=EUspDBNiAAAA:8 a=ruhtLSfl90xYY3NouLkA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=x9snwWr2DeNwDh03kgHS:22 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2026-01-16_02,2026-01-15_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 impostorscore=0 malwarescore=0 phishscore=0 priorityscore=1501 bulkscore=0 suspectscore=0 adultscore=0 spamscore=0 clxscore=1015 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2512120000 definitions=main-2601160060 On 1/16/2026 3:52 AM, Rob Clark wrote: > On Wed, Dec 31, 2025 at 12:45 AM Akhil P Oommen > wrote: >> >> This is a respin of an old series [1] that aimed to add support for >> Adreno 612 GPU found in SM6150/QCS615 chipsets. In this version, we >> have consolidated the previously separate series for DT and driver >> support, along with some significant rework. >> >> Regarding A612 GPU, it falls under ADRENO_6XX_GEN1 family and is a cut >> down version of A615 GPU. A612 has a new IP called Reduced Graphics >> Management Unit or RGMU, a small state machine which helps to toggle >> GX GDSC (connected to CX rail) to implement the IFPC feature. Unlike a >> full-fledged GMU, the RGMU does not support features such as clock >> control, resource voting via RPMh, HFI etc. Therefore, we require linux >> clock driver support similar to gmu-wrapper implementations to control >> gpu core clock and GX GDSC. >> >> In this series, the description of RGMU hardware in devicetree is more >> complete than in previous version. However, the RGMU core is not >> initialized from the driver as there is currently no need for it. We do >> perform a dummy load of RGMU firmware (now available in linux-firmware) >> to ensure that enabling RGMU core in the future won't break backward >> compatibility for users. >> >> Due to significant changes compared to the old series, all R-b tags have >> been dropped. Please review with fresh eyes. >> >> Last 3 patches are for Bjorn and the rest are for Rob Clark for pick up. > > I guess you meant the last 4 patches are for Bjorn? Yes, that is correct. I missed updating this sentence after including the GPU cooling related dt patch. -Akhil > > BR, > -R > >> >> [1] Driver: https://lore.kernel.org/lkml/20241213-a612-gpu-support-v3-1-0e9b25570a69@quicinc.com/ >> Devicetree: https://lore.kernel.org/lkml/fu4rayftf3i4arf6l6bzqyzsctomglhpiniljkeuj74ftvzlpo@vklca2giwjlw/ >> >> Signed-off-by: Akhil P Oommen >> --- >> Changes in v6: >> - Move the rgmu register range update from patch#8 to patch#6. >> - Capture trailers >> - Link to v5: https://lore.kernel.org/r/20251226-qcs615-spin-2-v5-0-354d86460ccb@oss.qualcomm.com >> >> Changes in v5: >> - Rebase on v6.19-rc2 >> - Make the reg list in A612 GPU's binding doc stricter (Krzysztof) >> - Link to v4: https://lore.kernel.org/r/20251204-qcs615-spin-2-v4-0-f5a00c5b663f@oss.qualcomm.com >> >> Changes in v4: >> - Rebased on top of next-20251204 tag >> - Added a new patch to simplify gpu dt schema (Krzysztof) >> - Added a new patch for GPU cooling support (Gaurav) >> - Updated the gpu/gmu register range in DT to be more accurate >> - Remove 290Mhz corner for GPU as that is not present in downstream >> - Link to v3: https://lore.kernel.org/r/20251122-qcs615-spin-2-v3-0-9f4d4c87f51d@oss.qualcomm.com >> >> Changes in v3: >> - Rebased on top of next-20251121 tag >> - Drop a612 driver support patch as it got picked up >> - Rename rgmu.yaml -> qcom,adreno-rgmu.yaml (Krzysztof) >> - Remove reg-names property for rgmu node (Krzysztof) >> - Use 'gmu' instead of 'rgmu' as node name (Krzysztof) >> - Describe cx_mem and cx_dgc register ranges (Krzysztof) >> - A new patch to retrieve gmu core reg resource by id >> - Link to v2: https://lore.kernel.org/r/20251107-qcs615-spin-2-v2-0-a2d7c4fbf6e6@oss.qualcomm.com >> >> Changes in v2: >> - Rebased on next-20251105 >> - Fix hwcg configuration (Dan) >> - Reuse a few gmu-wrapper routines (Konrad) >> - Split out rgmu dt schema (Krzysztof/Dmitry) >> - Fixes for GPU dt binding doc (Krzysztof) >> - Removed VDD_CX from rgmu dt node. Will post a separate series to >> address the gpucc changes (Konrad) >> - Fix the reg range size for adreno smmu node and reorder the properties (Konrad) >> - Link to v1: https://lore.kernel.org/r/20251017-qcs615-spin-2-v1-0-0baa44f80905@oss.qualcomm.com >> >> --- >> Akhil P Oommen (3): >> drm/msm/a6xx: Retrieve gmu core range by index >> dt-bindings: display/msm: gpu: Simplify conditional schema logic >> dt-bindings: display/msm: gpu: Document A612 GPU >> >> Gaurav Kohli (1): >> arm64: dts: qcom: talos: Add GPU cooling >> >> Jie Zhang (3): >> dt-bindings: display/msm/rgmu: Document A612 RGMU >> arm64: dts: qcom: talos: Add gpu and rgmu nodes >> arm64: dts: qcom: qcs615-ride: Enable Adreno 612 GPU >> >> Qingqing Zhou (1): >> arm64: dts: qcom: talos: add the GPU SMMU node >> >> .../devicetree/bindings/display/msm/gpu.yaml | 89 +++++++++--- >> .../bindings/display/msm/qcom,adreno-rgmu.yaml | 126 +++++++++++++++++ >> MAINTAINERS | 1 + >> arch/arm64/boot/dts/qcom/qcs615-ride.dts | 8 ++ >> arch/arm64/boot/dts/qcom/talos.dtsi | 149 +++++++++++++++++++++ >> drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 14 +- >> 6 files changed, 357 insertions(+), 30 deletions(-) >> --- >> base-commit: 2408853dde584f01950a0f976b743739cce30eca >> change-id: 20251015-qcs615-spin-2-ed45b0deb998 >> >> Best regards, >> -- >> Akhil P Oommen >>