From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E4D9330CDBD for ; Tue, 3 Feb 2026 20:14:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770149686; cv=none; b=WwOkD7nahJZC2lLynuo1pmuVaUpTqrtfTYYbKLkM9Kc49OnmfiF6CTSJiSJ8eAL9XvJiWenccFMleiZd1W/lSQ27DPpmEpP8acYyrNRnUvzchdtW8mqWMAOKxcNpsAzQiX8TAfXlNTEaJAZgqhIlvO9rqftnNyQCS0yMkIJc+nE= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770149686; c=relaxed/simple; bh=jqqQkwbDLQbHPQqBWCaSLILFXcpkGXuO6VnAcQNCWIk=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=YKCG1B7mgV0DO9eexqUtKheBzmKHrC4+w8QgEOpyqzvAvwQet6W1cXlFmsZ0zsSubRzQqXYfZUw83YMN8H+Q1uiAf/+hVBJhA6C14Pi4FZ3cVcz7VJ8F1p/SMImlTI3UBtqNMjEqjHigGzkp6bQiv00ScT63A4o/T+fqgz7+eck= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=ZeftixxV; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="ZeftixxV" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 19D0FC116D0; Tue, 3 Feb 2026 20:14:45 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1770149685; bh=jqqQkwbDLQbHPQqBWCaSLILFXcpkGXuO6VnAcQNCWIk=; h=Date:Subject:To:Cc:References:From:In-Reply-To:From; b=ZeftixxVgD/dZoIEoqmxd/lp0dMyJb0Bc8WqhLGaV1S2wDEVwTmd1rQJYyRXYY45w X8IqPqRJF43dhVkUMI/w3Sqatfwm9mZftb51TylkBVhIm6OHS3jC7/g3Mxxk+j4pFl eDyo++Ncnm4dNyzkgenSHaSWOIcJ3+94wAGD9SnTwpp97rcV0w3HDAF7grX8mQCZGk C4MpDv4kKuEczq8RGEpaMsq3Kfhb97YWYgOxGegjOIPHlvj/RbtadFLBVD8Bql4RPA wa0xggmUiWK3fm7x8Zllh0jyJTKVjelaHSxeBTCXNWN6Pr64xGCXQyg7Av6NXRkCfm ZeNMQyft0qzOg== Message-ID: Date: Tue, 3 Feb 2026 15:14:46 -0500 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [RFC PATCH] workqueue: Automatic affinity scope fallback for single-pod topologies To: Tejun Heo Cc: jiangshanlai@gmail.com, linux-kernel@vger.kernel.org, Chuck Lever References: <20260203143744.16578-1-cel@kernel.org> Content-Language: en-US From: Chuck Lever Organization: kernel.org In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit On 2/3/26 2:10 PM, Tejun Heo wrote: > Hello, > > On Tue, Feb 03, 2026 at 09:37:44AM -0500, Chuck Lever wrote: >> On such systems WQ_AFFN_CACHE, WQ_AFFN_SMT, and WQ_AFFN_NUMA scopes all >> collapse to a single pod. > > WQ_AFFN_SMT should be on CPU core boundaries, right? > >> Add wq_effective_affn_scope() to detect when a selected affinity scope >> provides only one pod despite having multiple CPUs, and automatically >> fall back to a finer-grained scope. This ensures reasonable lock >> distribution without requiring manual configuration via the >> workqueue.default_affinity_scope parameter or per-workqueue sysfs >> tuning. >> >> The fallback is conservative: it triggers only when a scope degenerates >> to exactly one pod, and respects explicitly configured (non-default) >> scopes. > > While I understand the problem, I don't think dropping down to core boundary > for unbound workqueues by default makes sense. That may help with some use > cases but cause problem with others. I've never seen a case where it doesn't help. In order to craft an alternative, I'll need to have some examples to avoid. Is it only the SMT case that is concerning? > Given that WQ_AFFN_CACHE is the same as > WQ_AFFN_NUMA on these machines, maybe we can shard it automatically > according to some heuristics or maybe we can introduce another affinity > level between CACHE and SMT which is sharded on machines with too many CPUs > in a single cache domain. -- Chuck Lever