From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756104AbdJJJio (ORCPT ); Tue, 10 Oct 2017 05:38:44 -0400 Received: from mail-pf0-f193.google.com ([209.85.192.193]:37657 "EHLO mail-pf0-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756006AbdJJJim (ORCPT ); Tue, 10 Oct 2017 05:38:42 -0400 X-Google-Smtp-Source: AOwi7QBq6zbumXKo5UC0dwKUgSj432Sy2hGUjb9+7+KBI08p7uZiQZtaJxE8rDLa4FK0H8qMk2zOJw== Subject: Re: [PATCH v3 5/9] soc: mediatek: pwrap: add pwrap_write32 for writing in 32-bit mode To: sean.wang@mediatek.com, robh+dt@kernel.org, mark.rutland@arm.com, lgirdwood@gmail.com, broonie@kernel.org, jamesjj.liao@mediatek.com, henryc.chen@mediatek.com, devicetree@vger.kernel.org, linux-mediatek@lists.infradead.org Cc: chen.zhong@mediatek.com, chenglin.xu@mediatek.com, linux-kernel@vger.kernel.org References: <236a04acb383fc655549bc345a16a2d015e5727d.1502779753.git.sean.wang@mediatek.com> From: Matthias Brugger Message-ID: Date: Tue, 10 Oct 2017 11:38:36 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.3.0 MIME-Version: 1.0 In-Reply-To: <236a04acb383fc655549bc345a16a2d015e5727d.1502779753.git.sean.wang@mediatek.com> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 08/15/2017 11:09 AM, sean.wang@mediatek.com wrote: > From: Sean Wang > > Some regulators such as MediaTek MT6380 also has to be written in > 32-bit mode. So the patch adds pwrap_write32, rename old pwrap_write > into pwrap_write16 and one additional function pointer is introduced > for increasing flexibility allowing the determination which mode is > used by the pwrap slave detection through device tree. > > Signed-off-by: Chenglin Xu > Signed-off-by: Chen Zhong > Signed-off-by: Sean Wang > --- > drivers/soc/mediatek/mtk-pmic-wrap.c | 63 +++++++++++++++++++++++++++--------- > 1 file changed, 47 insertions(+), 16 deletions(-) > > diff --git a/drivers/soc/mediatek/mtk-pmic-wrap.c b/drivers/soc/mediatek/mtk-pmic-wrap.c > index 7cd581b..9d1f4c6 100644 > --- a/drivers/soc/mediatek/mtk-pmic-wrap.c > +++ b/drivers/soc/mediatek/mtk-pmic-wrap.c > @@ -506,6 +506,7 @@ struct pwrap_slv_type { > * which type is used by the detection through device tree. > */ > int (*pwrap_read)(struct pmic_wrapper *wrp, u32 adr, u32 *rdata); > + int (*pwrap_write)(struct pmic_wrapper *wrp, u32 adr, u32 wdata); > }; > > struct pmic_wrapper { > @@ -600,22 +601,6 @@ static int pwrap_wait_for_state(struct pmic_wrapper *wrp, > } while (1); > } > > -static int pwrap_write(struct pmic_wrapper *wrp, u32 adr, u32 wdata) > -{ > - int ret; > - > - ret = pwrap_wait_for_state(wrp, pwrap_is_fsm_idle); > - if (ret) { > - pwrap_leave_fsm_vldclr(wrp); > - return ret; > - } > - > - pwrap_writel(wrp, (1 << 31) | ((adr >> 1) << 16) | wdata, > - PWRAP_WACS2_CMD); > - > - return 0; > -} > - > static int pwrap_read16(struct pmic_wrapper *wrp, u32 adr, u32 *rdata) > { > int ret; > @@ -672,6 +657,49 @@ static int pwrap_read(struct pmic_wrapper *wrp, u32 adr, u32 *rdata) > return wrp->slave->pwrap_read(wrp, adr, rdata); > } > > +static int pwrap_write16(struct pmic_wrapper *wrp, u32 adr, u32 wdata) > +{ > + int ret; > + > + ret = pwrap_wait_for_state(wrp, pwrap_is_fsm_idle); > + if (ret) { > + pwrap_leave_fsm_vldclr(wrp); > + return ret; > + } > + > + pwrap_writel(wrp, (1 << 31) | ((adr >> 1) << 16) | wdata, > + PWRAP_WACS2_CMD); > + > + return 0; > +} > + > +static int pwrap_write32(struct pmic_wrapper *wrp, u32 adr, u32 wdata) > +{ > + int ret, msb, rdata; > + > + for (msb = 0; msb < 2; msb++) { > + ret = pwrap_wait_for_state(wrp, pwrap_is_fsm_idle); > + if (ret) { > + pwrap_leave_fsm_vldclr(wrp); > + return ret; > + } > + > + pwrap_writel(wrp, (1 << 31) | (msb << 30) | (adr << 16) | > + ((wdata >> (msb * 16)) & 0xffff), > + PWRAP_WACS2_CMD); > + > + if (!msb) > + pwrap_read(wrp, adr, &rdata); Just so that I understand, you have to read back the half-written register before you can write the second part? Other then that it looks fine to me. Regards, Matthias