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Wed, 10 Sep 2025 03:57:28 -0700 (PDT) X-Google-Smtp-Source: AGHT+IEAd+1N4v2AfeNoYwFOl+bjuiXGrs3u3rlBpUd9S2XvNr6uBsVx1PO/O6R0zKylE+mie5ldNw== X-Received: by 2002:a05:6a21:6d9e:b0:253:2fae:5287 with SMTP id adf61e73a8af0-2533e18d170mr20798121637.26.1757501848153; Wed, 10 Sep 2025 03:57:28 -0700 (PDT) Received: from [10.217.219.207] ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-775f4976bcasm2333665b3a.100.2025.09.10.03.57.23 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 10 Sep 2025 03:57:27 -0700 (PDT) Message-ID: Date: Wed, 10 Sep 2025 16:27:23 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 4/5] i2c: qcom-cci: Add OPP table support and enforce FAST_PLUS requirements To: Konrad Dybcio , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bryan O'Donoghue , Loic Poulain , Robert Foss , Andi Shyti Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-i2c@vger.kernel.org, Konrad Dybcio References: <20250904-topic-cci_updates-v1-0-d38559692703@oss.qualcomm.com> <20250904-topic-cci_updates-v1-4-d38559692703@oss.qualcomm.com> Content-Language: en-US From: Mukesh Savaliya In-Reply-To: <20250904-topic-cci_updates-v1-4-d38559692703@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Authority-Analysis: v=2.4 cv=Yv8PR5YX c=1 sm=1 tr=0 ts=68c1599a cx=c_pps a=rEQLjTOiSrHUhVqRoksmgQ==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=yJojWOMRYYMA:10 a=EUspDBNiAAAA:8 a=x1LqVQa0TBYraXIDtAYA:9 a=QEXdDO2ut3YA:10 a=2VI0MkxyNR6bbpdq8BZq:22 X-Proofpoint-GUID: haC0PMXtFwWrbxtfGvio6GP_cMGmL2s5 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwOTA2MDAxOCBTYWx0ZWRfX77MpB7CxYigX Pe/BL2assGEY3wLDyiCRLx5vrpl77j1hS9GshIUHbvFslmO6o8GZBtvRFOytcoA7e2bKJM4VIcU GRqRHlaZu7lq5I4JC4vWvlR2jJOf3RMq9YEV5DWi5uKnTzXv6ElZX9S2GS/suvoroaRDgzhUD4C BIuwUHAW5qw8c6JZUv/4lHzOB5jJFdiRNiw9mXnsw3gg2XwaX6BobR9/YK5/e5+yXjWuJCsaNH9 E96y0gi6d2Tv+Oc4gHfucVUwzeKdKJANxK8+Wb77AURo3siNjQCK9IYjlG+GsitC4DHwN6ezzw6 GW2WMFk8QnTTNO07KdrbF4EylzS6bRol5rYjDY3YAzhsQ/PNGDyh5B6XLykUptMQSdvVQIkyBTf xYAcsUg7 X-Proofpoint-ORIG-GUID: haC0PMXtFwWrbxtfGvio6GP_cMGmL2s5 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1117,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-09-09_03,2025-09-10_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 malwarescore=0 suspectscore=0 phishscore=0 clxscore=1015 spamscore=0 priorityscore=1501 impostorscore=0 adultscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2507300000 definitions=main-2509060018 On 9/4/2025 8:01 PM, Konrad Dybcio wrote: > From: Konrad Dybcio > > The CCI clock has voltage requirements, which need to be described > through an OPP table. > > The 1 MHz FAST_PLUS mode requires the CCI core clock runs at 37,5 MHz Typo: 37.5 MHz> (which is a value common across all SoCs), since it's not possible to > reach the required timings with the default 19.2 MHz rate. > > Address both issues by introducing an OPP table and using it to vote > for the faster rate. > > Signed-off-by: Konrad Dybcio > --- [...]