From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752151AbdLDXSu (ORCPT ); Mon, 4 Dec 2017 18:18:50 -0500 Received: from foss.arm.com ([217.140.101.70]:42804 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751200AbdLDXSt (ORCPT ); Mon, 4 Dec 2017 18:18:49 -0500 Subject: Re: [linux-sunxi] [PATCH 2/2] clk: sunxi-ng: sun50i: a64: Add 2x fixed post-divider to MMC module clocks To: wens@csie.org, Maxime Ripard , Michael Turquette , Stephen Boyd References: <20171204051912.7485-1-wens@csie.org> <20171204051912.7485-3-wens@csie.org> Cc: linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, linux-sunxi@googlegroups.com From: =?UTF-8?Q?Andr=c3=a9_Przywara?= Organization: ARM Ltd. Message-ID: Date: Mon, 4 Dec 2017 23:18:15 +0000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:45.0) Gecko/20100101 Thunderbird/45.8.0 MIME-Version: 1.0 In-Reply-To: <20171204051912.7485-3-wens@csie.org> Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 04/12/17 05:19, Chen-Yu Tsai wrote: > On the A64, the MMC module clocks are fixed in the new timing mode, > i.e. they do not have a bit to select the mode. These clocks have > a 2x divider somewhere between the clock and the MMC module. > > To be consistent with other SoCs supporting the new timing mode, > we model the 2x divider as a fixed post-divider on the MMC module > clocks. > > This patch adds the post-dividers to the MMC clocks. > > Signed-off-by: Chen-Yu Tsai Reviewed-by: Andre Przywara Cheers, Andre > --- > drivers/clk/sunxi-ng/ccu-sun50i-a64.c | 57 +++++++++++++++++++++++------------ > 1 file changed, 37 insertions(+), 20 deletions(-) > > diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c > index 2bb4cabf802f..ee9c12cf3f08 100644 > --- a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c > +++ b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c > @@ -400,28 +400,45 @@ static SUNXI_CCU_MP_WITH_MUX_GATE(nand_clk, "nand", mod0_default_parents, 0x080, > BIT(31), /* gate */ > 0); > > +/* > + * MMC clocks are the new timing mode (see A83T & H3) variety, but without > + * the mode switch. This means they have a 2x post divider between the clock > + * and the MMC module. This is not documented in the manual, but is taken > + * into consideration when setting the mmc module clocks in the BSP kernel. > + * Without it, MMC performance is degraded. > + * > + * We model it here to be consistent with other SoCs supporting this mode. > + * The alternative would be to add the 2x multiplier when setting the MMC > + * module clock in the MMC driver, just for the A64. > + */ > static const char * const mmc_default_parents[] = { "osc24M", "pll-periph0-2x", > "pll-periph1-2x" }; > -static SUNXI_CCU_MP_WITH_MUX_GATE(mmc0_clk, "mmc0", mmc_default_parents, 0x088, > - 0, 4, /* M */ > - 16, 2, /* P */ > - 24, 2, /* mux */ > - BIT(31), /* gate */ > - 0); > - > -static SUNXI_CCU_MP_WITH_MUX_GATE(mmc1_clk, "mmc1", mmc_default_parents, 0x08c, > - 0, 4, /* M */ > - 16, 2, /* P */ > - 24, 2, /* mux */ > - BIT(31), /* gate */ > - 0); > - > -static SUNXI_CCU_MP_WITH_MUX_GATE(mmc2_clk, "mmc2", mmc_default_parents, 0x090, > - 0, 4, /* M */ > - 16, 2, /* P */ > - 24, 2, /* mux */ > - BIT(31), /* gate */ > - 0); > +static SUNXI_CCU_MP_WITH_MUX_GATE_POSTDIV(mmc0_clk, "mmc0", > + mmc_default_parents, 0x088, > + 0, 4, /* M */ > + 16, 2, /* P */ > + 24, 2, /* mux */ > + BIT(31), /* gate */ > + 2, /* post-div */ > + 0); > + > +static SUNXI_CCU_MP_WITH_MUX_GATE_POSTDIV(mmc1_clk, "mmc1", > + mmc_default_parents, 0x08c, > + 0, 4, /* M */ > + 16, 2, /* P */ > + 24, 2, /* mux */ > + BIT(31), /* gate */ > + 2, /* post-div */ > + 0); > + > +static SUNXI_CCU_MP_WITH_MUX_GATE_POSTDIV(mmc2_clk, "mmc2", > + mmc_default_parents, 0x090, > + 0, 4, /* M */ > + 16, 2, /* P */ > + 24, 2, /* mux */ > + BIT(31), /* gate */ > + 2, /* post-div */ > + 0); > > static const char * const ts_parents[] = { "osc24M", "pll-periph0", }; > static SUNXI_CCU_MP_WITH_MUX_GATE(ts_clk, "ts", ts_parents, 0x098, >