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[78.11.189.27]) by smtp.gmail.com with ESMTPSA id t9-20020ac25489000000b00499bf7605afsm1548615lfk.143.2022.09.23.11.05.20 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 23 Sep 2022 11:05:21 -0700 (PDT) Message-ID: Date: Fri, 23 Sep 2022 20:05:19 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.3.0 Subject: Re: [PATCH v3 2/2] pinctrl: nuvoton: add NPCM8XX pinctrl and GPIO driver Content-Language: en-US To: Tomer Maimon , avifishman70@gmail.com, tali.perry1@gmail.com, joel@jms.id.au, venture@google.com, yuenn@google.com, benjaminfair@google.com, linus.walleij@linaro.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, j.neuschaefer@gmx.net, zhengbin13@huawei.com Cc: openbmc@lists.ozlabs.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org References: <20220921095053.88658-1-tmaimon77@gmail.com> <20220921095053.88658-3-tmaimon77@gmail.com> From: Krzysztof Kozlowski In-Reply-To: <20220921095053.88658-3-tmaimon77@gmail.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 21/09/2022 11:50, Tomer Maimon wrote: > Add pinctrl and GPIO controller driver support to Arbel BMC NPCM8XX SoC. > > Arbel BMC NPCM8XX pinctrl driver based on Poleg NPCM7XX, except the > pin mux mapping difference the NPCM8XX GPIO supports adjust debounce > period time. > > Signed-off-by: Tomer Maimon > --- > drivers/pinctrl/nuvoton/Kconfig | 14 + > drivers/pinctrl/nuvoton/Makefile | 1 + > drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c | 2485 +++++++++++++++++++++ > 3 files changed, 2500 insertions(+) > create mode 100644 drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c > > diff --git a/drivers/pinctrl/nuvoton/Kconfig b/drivers/pinctrl/nuvoton/Kconfig > index 852b0d0eb08e..3a67cdb346ab 100644 > --- a/drivers/pinctrl/nuvoton/Kconfig > +++ b/drivers/pinctrl/nuvoton/Kconfig > @@ -31,3 +31,17 @@ config PINCTRL_NPCM7XX > help > Say Y here to enable pin controller and GPIO support > for Nuvoton NPCM750/730/715/705 SoCs. > + > +config PINCTRL_NPCM8XX > + tristate "Pinctrl and GPIO driver for Nuvoton NPCM8XX" > + depends on ARCH_NPCM || COMPILE_TEST > + select PINMUX > + select PINCONF > + select GENERIC_PINCONF > + select GPIOLIB > + select GPIO_GENERIC > + select GPIOLIB_IRQCHIP > + help > + Say Y or M here to enable pin controller and GPIO support for > + the Nuvoton NPCM8XX SoC. This is strongly recommended when > + building a kernel that will run on this chip. > \ No newline at end of file Fix warning. Best regards, Krzysztof