From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.11]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8051C369D66 for ; Sat, 25 Jul 2026 09:32:54 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.11 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784971978; cv=none; b=XEGCM3lZe4TXKVpKUO6nwCAVDEE5aJEdgkeBSg4hGX7uf4tCXay6GxnsezpU+yCTIgd1ilKSu5YPjiS7GZBQ3hJPoK0EK9kJHyIHM4Xg6KVQOE6Zod7yhmByyMDffA7/wkZ0EgpS6beDuAZ0J21G1LHX3reY+JRgvOZ5hX/PCnA= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784971978; c=relaxed/simple; bh=sSFRPkEqYmzD7CYgptwqGrU43JKc25CEPrOHhpVArWE=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=kq20afOoSD0FYsxJz0/TPJUwxQh1UQpoOzjEzl6QBcfmV1rzylBihwfMTSNOoiJ8L6tMe8V8IuvIff6kT73vfsNSjFV4zvnZr5iBAGvTQm/uBbOceapLn9DGFmp62w2LGnK+zvE5fwz1c7QOZlnWuaz9D6AmUBq5/L/ooeTsoYk= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=aIaMfGwS; arc=none smtp.client-ip=198.175.65.11 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="aIaMfGwS" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1784971974; x=1816507974; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=sSFRPkEqYmzD7CYgptwqGrU43JKc25CEPrOHhpVArWE=; b=aIaMfGwSgdjOtYnfUATgB9WAzW2UFfQWzfvab2FYvNe/vcllS2ykF5dO DOme3QZdEGW5NyyTDP+b5axDJRy3KvXnkgWmCHOtYA1PKjfZCHjVAQA5C YL1B5SU81jQoTyJyL4YuFIZm/vRELiMaR1iz5e9WV2AlW1ccEuOWmzoMr emJ2sMzzfZYQox50IrhxRBdCfow1RiYwaq05IycFqYvN9l5GWNxiTTKXW 3PzWsEohZmgU7Avd+ODAHphHaSGzMSTU0Z0+O2DfkDrhAeRgqSQYU+NbW GWl9O7357oUAAaBBlTT9C6MSzTAIm1PhZW08hiGixaMxkFoyV2cU1yt7T w==; X-CSE-ConnectionGUID: ZQzKjL/sSiiHVxHpnTgZxg== X-CSE-MsgGUID: 7d2DJlRyQsCKpXvDZreYzA== X-IronPort-AV: E=McAfee;i="6800,10657,11855"; a="95979031" X-IronPort-AV: E=Sophos;i="6.25,184,1779174000"; d="scan'208";a="95979031" Received: from fmviesa005.fm.intel.com ([10.60.135.145]) by orvoesa103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Jul 2026 02:32:51 -0700 X-CSE-ConnectionGUID: I+bVKFvrS3W4QnyBvWYwSg== X-CSE-MsgGUID: v/XUEDStRLqQACrk0WzluA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.25,184,1779174000"; d="scan'208";a="263922553" Received: from chenyu-dev.sh.intel.com ([10.239.62.107]) by fmviesa005.fm.intel.com with ESMTP; 25 Jul 2026 02:32:48 -0700 From: Chen Yu To: tony.luck@intel.com, reinette.chatre@intel.com Cc: tglx@kernel.org, bp@alien8.de, mingo@redhat.com, dave.hansen@linux.intel.com, hpa@zytor.com, fenghuay@nvidia.com, babu.moger@amd.com, chen.yu@linux.dev, x86@kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v6 4/9] x86/resctrl: Attach ACPI ERDT information to L3 mon domain on CPU online Date: Sat, 25 Jul 2026 17:23:04 +0800 Message-Id: X-Mailer: git-send-email 2.25.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Reading LLC occupancy counters via MMIO requires the per-domain ERDT information, parsed earlier from the ACPI ERDT table, to be reachable from the resctrl L3 monitoring domain. Nothing links the two yet, so the monitoring code cannot locate the MMIO registers of a domain. ERDT and CPUID enumerate CPU-to-L3-domain membership independently: CPUID leaf 4 describes the L3 cache topology, while the firmware CACD sub-table lists the CPUs of each ERDT domain. Both views must agree on a CPU's L3 domain for that CPU to be monitored safely. When a CPU comes online, validate that firmware and CPUID agree on its L3 domain before adding it to a resctrl monitoring domain. Exclude the CPU from all monitoring domains on a mismatch because a topology inconsistency between ERDT and CPUID indicates a firmware defect that makes the CPU's domain placement unreliable for any resource. Otherwise attach the matching ERDT domain information to the L3 monitoring domain so that later code can read monitoring data via ERDT and its sub-tables. Suggested-by: Reinette Chatre Signed-off-by: Chen Yu Tested-by: Hongyu Ning --- v5->v6: Call erdt_cpu_valid() in domain_add_cpu_mon() before the CPU is added to the domain cpu_mask, and bail out early on a mismatch. (Reinette Chatre) Drop the redundant pr_warn() in the caller, the callee already warns. (Reinette Chatre) Use list_for_each_entry(). (Reinette Chatre) Make the domain information pointer const instead of documenting it as read only in a comment. (Reinette Chatre) Adjust the ERDT/CPUID mismatch check that the CPUs disagrees with ERDT/CPUID domain is excluded from resctrl. (Reinette Chatre) --- arch/x86/kernel/cpu/resctrl/core.c | 11 ++++- arch/x86/kernel/cpu/resctrl/erdt.c | 66 ++++++++++++++++++++++++++ arch/x86/kernel/cpu/resctrl/internal.h | 5 ++ 3 files changed, 81 insertions(+), 1 deletion(-) diff --git a/arch/x86/kernel/cpu/resctrl/core.c b/arch/x86/kernel/cpu/resctrl/core.c index 23925bcd71d7..c2568b29474e 100644 --- a/arch/x86/kernel/cpu/resctrl/core.c +++ b/arch/x86/kernel/cpu/resctrl/core.c @@ -580,6 +580,9 @@ static void domain_add_cpu_mon(int cpu, struct rdt_resource *r) return; } + if (!erdt_cpu_valid(cpu)) + return; + hdr = resctrl_find_domain(&r->mon_domains, id, &add_pos); if (hdr) cpumask_set_cpu(cpu, &hdr->cpu_mask); @@ -589,8 +592,14 @@ static void domain_add_cpu_mon(int cpu, struct rdt_resource *r) /* Update the mbm_assign_mode state for the CPU if supported */ if (r->mon.mbm_cntr_assignable) resctrl_arch_mbm_cntr_assign_set_one(r); - if (!hdr) + if (!hdr) { l3_mon_domain_setup(cpu, id, r, add_pos); + hdr = resctrl_find_domain(&r->mon_domains, id, NULL); + } + + if (hdr) + erdt_l3_mon_domain_setup(cpu, hdr); + break; case RDT_RESOURCE_PERF_PKG: if (!hdr) diff --git a/arch/x86/kernel/cpu/resctrl/erdt.c b/arch/x86/kernel/cpu/resctrl/erdt.c index 8998cae47090..6257869d0db2 100644 --- a/arch/x86/kernel/cpu/resctrl/erdt.c +++ b/arch/x86/kernel/cpu/resctrl/erdt.c @@ -207,6 +207,72 @@ static __init bool parse_rmdd_table(struct acpi_subtbl_hdr_16 *rmdd_hdr) return false; } +bool erdt_cpu_valid(int cpu) +{ + struct erdt_domain_info *d; + int dom_id; + + if (!erdt_enabled) + return true; + + dom_id = get_cpu_cacheinfo_id(cpu, RESCTRL_L3_CACHE); + if (dom_id < 0) + return true; + + /* + * Find the erdt_domain_info that contains this CPU, + * check if all CPUs in erdt_domain_info's cpumask + * have the same id(L3 id). + * + * For example, erdt_domain_info reports: + * domain0: CPU0, CPU2, domain1: CPU1, CPU3 + * rdt_domain_hdr reports: + * domain0: CPU0, CPU1, domain1: CPU2, CPU3 + * As a result, CPU1, CPU2 should not be covered by resctrl. + */ + list_for_each_entry(d, &domain_info_list, entry) { + + if (cpumask_test_cpu(cpu, &d->cpu_mask)) { + if (d->dom_id == -1) { + d->dom_id = dom_id; + } else if (d->dom_id != dom_id) { + pr_warn(FW_BUG "CPU%d's id=%d not equal to CACD domain(%*pbl) id=%d, skip this CPU\n", + cpu, dom_id, cpumask_pr_args(&d->cpu_mask), d->dom_id); + + return false; + } + + return true; + } + } + + pr_warn(FW_BUG "Cannot find CACD domain for CPU%d\n", cpu); + return false; +} + +/* + * Associate ERDT table information with this domain. + */ +void erdt_l3_mon_domain_setup(int cpu, struct rdt_domain_hdr *hdr) +{ + struct rdt_hw_l3_mon_domain *hw_dom; + struct erdt_domain_info *d; + + if (!erdt_enabled) + return; + + hw_dom = resctrl_to_arch_mon_dom(container_of(hdr, struct rdt_l3_mon_domain, hdr)); + + list_for_each_entry(d, &domain_info_list, entry) { + if (cpumask_test_cpu(cpu, &d->cpu_mask)) { + /* Assign the ERDT information to hw_dom */ + if (!hw_dom->d_info) + hw_dom->d_info = d; + return; + } + } +} + void erdt_exit(void) { struct erdt_domain_info *d, *tmp; diff --git a/arch/x86/kernel/cpu/resctrl/internal.h b/arch/x86/kernel/cpu/resctrl/internal.h index bdff3ea36e62..bd437c3e5bf0 100644 --- a/arch/x86/kernel/cpu/resctrl/internal.h +++ b/arch/x86/kernel/cpu/resctrl/internal.h @@ -99,14 +99,19 @@ struct rdt_hw_ctrl_domain { * @arch_mbm_states: Per-event pointer to the MBM event's saved state. * An MBM event's state is an array of struct arch_mbm_state * indexed by RMID on x86. + * @d_info: ERDT table information of this domain * * Members of this structure are accessed via helpers that provide abstraction. */ struct rdt_hw_l3_mon_domain { struct rdt_l3_mon_domain d_resctrl; struct arch_mbm_state *arch_mbm_states[QOS_NUM_L3_MBM_EVENTS]; + const struct erdt_domain_info *d_info; }; +bool erdt_cpu_valid(int cpu); +void erdt_l3_mon_domain_setup(int cpu, struct rdt_domain_hdr *hdr); + static inline struct rdt_hw_ctrl_domain *resctrl_to_arch_ctrl_dom(struct rdt_ctrl_domain *r) { return container_of(r, struct rdt_hw_ctrl_domain, d_resctrl); -- 2.25.1