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[103.229.16.4]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2dafe62d7c2sm11955965ad.29.2026.09.03.08.31.45 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 03 Sep 2026 08:31:51 -0700 (PDT) Message-ID: Date: Thu, 3 Sep 2026 23:31:43 +0800 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 08/12] clk: qcom: ipq-cmn-pll: Add EPHY-RAW clock support To: Abel Vesa Cc: Bjorn Andersson , Michael Turquette , Stephen Boyd , Brian Masney , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, quic_kkumarcs@quicinc.com, quic_linchen@quicinc.com, quic_leiwei@quicinc.com, quic_suruchia@quicinc.com References: <20260814-qcom_ipq5210_cmnpll-v3-0-21c3db378611@oss.qualcomm.com> <20260814-qcom_ipq5210_cmnpll-v3-8-21c3db378611@oss.qualcomm.com> Content-Language: en-US From: Jie Luo In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTAzMDEzNSBTYWx0ZWRfX5PUHaJkSMeah qEngA4/qSnuOd9eRpg42aQrALk37keKQbV+qW8tlC1j5qUd8pyiHb0MImEY9CSpBUx+yc1OQ+qn Jx8+QIcXR7eJhANGBOo5kE+qAU60MO2gx1ezkf0pNM6igTXoZIsrHx0X0gBirl26h5nJYU2jskn Zo9qTxHTjZ/pN/he9B68yt620SDTphT2G/fnbOV4Ae9J3gRMvHODGPifI1KdKk6cPrtA/7UBDzJ uLlL7TgNvf3UOvd5Tyvlhcpxo16F0Wg0sJh2e82x9RFWKbHEQp22erPCBePMVA57xS/6AhUQ8xZ VzrdZTDj2VYcwOpMd/oepEBiHOdug0Lo9M5y3d68sfR2CbX088DGidSjU78tKjvg8BNsw+AsFay u+HgDFS6Oc8dh4OMdXARAGW3sSA8sIvUBdRHkitE9yR4KtWxnQTK6bn+A0eqyIi19rRQ8RjQ/Lc 5MyCA1ldOVyyBGvZPtw== X-Proofpoint-ORIG-GUID: KHMDi9HNt4jiJyZztnQ5t1pnHMnYVIHO X-Proofpoint-Spam-Info: AW1haW4tMjYwOTAzMDEzNSBTYWx0ZWRfXxC0CbCSWeFYU 2GFLccA0Tj5/4mwGJmPX6s6z1/xRMpfkmmtsWlfDT16yw71l1FK3fWR+BRhZP5T/LZ+UXFaOAEw Be5qVo3C8GKCJgZsWb3X4i5MVTuaoTE= X-Proofpoint-GUID: KHMDi9HNt4jiJyZztnQ5t1pnHMnYVIHO X-Authority-Analysis: v=2.4 cv=J4GaKgnS c=1 sm=1 tr=0 ts=6a9992e9 cx=c_pps a=cmESyDAEBpBGqyK7t0alAg==:117 a=nuhDOHQX5FNHPW3J6Bj6AA==:17 a=IkcTkHD0fZMA:10 a=VdqzKS8jKosA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=DJpcGTmdVt4CTyJn9g5Z:22 a=bLGlZ6Hhwxh5CS4LpkgA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=1OuFwYUASf3TG4hYMiVC:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-03_04,2026-09-03_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 bulkscore=0 suspectscore=0 phishscore=0 clxscore=1015 spamscore=0 lowpriorityscore=0 priorityscore=1501 adultscore=0 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2609030135 On 9/3/2026 9:08 PM, Abel Vesa wrote: > On 26-08-14 05:48:18, Luo Jie wrote: >> The EPHY-RAW clock is an IPQ5210-specific output from the CMN PLL that >> provides the raw reference clock to the SoC-integrated Ethernet PHY >> (EPHY), which supports up to 2.5G link speed. The output frequency is >> selected via bit 10 (CMN_PLL_GEPHY_312P5M_125M_SEL) of the >> CMN_PLL_PON_CONFIG register: >> >> - 0: 125 MHz - for 1G/100M/10M link speed >> - 1: 312.5 MHz - for 2.5G link speed >> >> Parent it on cmn_pll_div2, like the rest of IPQ5210's output clocks, >> for clock-tree consistency. This is functionally identical: the >> output rate is purely register-bit-selected and never depends on the >> parent rate. > > So it is not a slice of the cmn_pll_div2 then. What is the actual source > of it then, in HW? Thanks for pointing this out. The wording is confusing. The EPHY-RAW clock is sourced from the CMN PLL /2 path in hardware, but its output rate is selected by the PLL/MUX logic controlled by CMN_PLL_GEPHY_312P5M_125M_SEL. I will drop the “never depends on the parent rate” wording to avoid implying that it is not sourced from cmn_pll_div2.