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[103.229.18.19]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-823098cb1basm751620b3a.32.2026.01.21.22.45.19 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 21 Jan 2026 22:45:23 -0800 (PST) Message-ID: Date: Thu, 22 Jan 2026 12:15:17 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v5 3/4] arm64: dts: qcom: Introduce Glymur base dtsi To: Dmitry Baryshkov Cc: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Jyothi Kumar Seerapu , Maulik Shah , Sibi Sankar , Taniya Das , Kamal Wadhwa , Qiang Yu , Manaf Meethalavalappu Pallikunhi , Jishnu Prakash , Abel Vesa References: <20260122-upstream_v3_glymur_introduction-v5-0-8ba76c354e9a@oss.qualcomm.com> <20260122-upstream_v3_glymur_introduction-v5-3-8ba76c354e9a@oss.qualcomm.com> Content-Language: en-US From: Pankaj Patil In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMTIyMDA0MyBTYWx0ZWRfX8iswfmIKmntg iTmhh07uaJRMBj5J2/imSXMzOQVeMwGYvEaTL6sW5/FNjufe8/R0ufye4aewshXdm/2txiVhbRB n6A13p0nm2gGRpydw4tlePbWxcdize1wKtgfQm+pe7zZ023e7hAuvYM0N1wUrUXOTX8kTh5TIOx vx3QJNtKvK2slRMLeJGAsxZ2TLpTZ+oz9CfubLqXAjqGaICzrjqZ5+nqsDPUPhjRdu0rkwZiCil e4OY/++kF/Mrwj/oYNzHD0tNIj4B8oZVlgU00WLFOfHKpdqewBn4R+CzXefkq+iJgyOa64GFRwk oD+Hc5cXd4yahejtLnH2iu7Q5SYS7jjigmK+vwLiF1G0e/vw5Zhr3KLNnfrj5HFUUBDSB10aIx6 X6mpkYRnAHCKpqAS2cvj8Y4yqZ34PKNRoTYC0/Ow+8+R8RjBElcsEhGihuIL1Ip2s46cSNTXrK+ HxY2UW8cmZ/Kzusd4Kg== X-Proofpoint-ORIG-GUID: qUH9hJL4O3elFLnMMNP7H3DOtLDgx-G_ X-Authority-Analysis: v=2.4 cv=UOjQ3Sfy c=1 sm=1 tr=0 ts=6971c785 cx=c_pps a=mDZGXZTwRPZaeRUbqKGCBw==:117 a=Ou0eQOY4+eZoSc0qltEV5Q==:17 a=IkcTkHD0fZMA:10 a=vUbySO9Y5rIA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=VwQbUJbxAAAA:8 a=KKAkSRfTAAAA:8 a=EUspDBNiAAAA:8 a=HCOLv22quEAogWv70kkA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=zc0IvFSfCIW2DFIPzwfm:22 a=cvBusfyB2V15izCimMoJ:22 X-Proofpoint-GUID: qUH9hJL4O3elFLnMMNP7H3DOtLDgx-G_ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.20,FMLib:17.12.100.49 definitions=2026-01-21_04,2026-01-20_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 phishscore=0 suspectscore=0 bulkscore=0 adultscore=0 clxscore=1015 lowpriorityscore=0 impostorscore=0 priorityscore=1501 spamscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2601150000 definitions=main-2601220043 On 1/22/2026 6:52 AM, Dmitry Baryshkov wrote: > On Thu, Jan 22, 2026 at 12:05:13AM +0530, Pankaj Patil wrote: >> Introduce the base device tree support for Glymur – Qualcomm's >> next-generation compute SoC. The new glymur.dtsi describes the core SoC >> components, including: >> >> - CPUs and CPU topology >> - Interrupt controller and TLMM >> - GCC,DISPCC and RPMHCC clock controllers >> - Reserved memory and interconnects >> - APPS and PCIe SMMU and firmware SCM >> - Watchdog, RPMHPD, APPS RSC and SRAM >> - PSCI and PMU nodes >> - QUPv3 serial engines >> - CPU power domains and idle states, plus SCMI/ SRAM pieces for CPU DVFS >> - PDP0 mailbox, IPCC and AOSS >> - Display clock controller >> - SPMI PMIC arbiter with SPMI0/1/2 buses >> - SMP2P nodes >> - TSENS and thermal zones (8 instances, 92 sensors) >> >> Add dtsi files for PMH0101, PMK8850, PMCX0102, SMB2370, PMH0104, >> PMH0110 along with temp-alarm and GPIO nodes needed on Glymur >> >> Enabled PCIe controllers and associated PHY to support boot to >> shell with nvme storage, >> List of PCIe instances enabled: >> >> - PCIe3b >> - PCIe4 >> - PCIe5 >> - PCIe6 >> >> Co-developed-by: Jyothi Kumar Seerapu >> Signed-off-by: Jyothi Kumar Seerapu >> Co-developed-by: Maulik Shah >> Signed-off-by: Maulik Shah >> Co-developed-by: Sibi Sankar >> Signed-off-by: Sibi Sankar >> Co-developed-by: Taniya Das >> Signed-off-by: Taniya Das >> Co-developed-by: Kamal Wadhwa >> Signed-off-by: Kamal Wadhwa >> Co-developed-by: Qiang Yu >> Signed-off-by: Qiang Yu >> Co-developed-by: Abel Vesa >> Signed-off-by: Abel Vesa >> Co-developed-by: Manaf Meethalavalappu Pallikunhi >> Signed-off-by: Manaf Meethalavalappu Pallikunhi >> Co-developed-by: Jishnu Prakash >> Signed-off-by: Jishnu Prakash >> Signed-off-by: Pankaj Patil >> --- >> arch/arm64/boot/dts/qcom/glymur.dtsi | 6122 ++++++++++++++++++++++++++ >> arch/arm64/boot/dts/qcom/pmcx0102.dtsi | 107 + >> arch/arm64/boot/dts/qcom/pmh0101.dtsi | 45 + >> arch/arm64/boot/dts/qcom/pmh0104-glymur.dtsi | 83 + >> arch/arm64/boot/dts/qcom/pmh0110-glymur.dtsi | 83 + >> arch/arm64/boot/dts/qcom/pmk8850.dtsi | 70 + >> arch/arm64/boot/dts/qcom/smb2370.dtsi | 45 + >> 7 files changed, 6555 insertions(+) >> >> diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi >> new file mode 100644 >> index 000000000000..c0ecc64202c7 >> --- /dev/null >> +++ b/arch/arm64/boot/dts/qcom/glymur.dtsi >> + >> + pmh0101-thermal { > > Why do we have PMIC thermal zones as a part of SoC DTSI? There were comments on v3 about moving them to out of board dts, https://lore.kernel.org/all/aUko20ORsgrlZrIn@linaro.org/ glymur-pmics.dtsi was dropped in v4, the changes were moved to glymur.dtsi > >> + polling-delay-passive = <100>; >> + thermal-sensors = <&pmh0101_temp_alarm>; >> + >> + trips { >> + trip0 { >> + temperature = <95000>; >> + hysteresis = <0>; >> + type = "passive"; >> + }; >> + >> + trip1 { >> + temperature = <115000>; >> + hysteresis = <0>; >> + type = "critical"; >> + }; >> + }; >> + }; >> + >> + pmcx0102-c0-thermal { >> + polling-delay-passive = <100>; >> + thermal-sensors = <&pmcx0102_c_e0_temp_alarm>; >> + >> + trips { >> + trip0 { >> + temperature = <95000>; >> + hysteresis = <0>; >> + type = "passive"; >> + }; >> + >> + trip1 { >> + temperature = <115000>; >> + hysteresis = <0>; >> + type = "critical"; >> + }; >> + }; >> + }; >> + >> + pmcx0102-d0-thermal { >> + polling-delay-passive = <100>; >> + thermal-sensors = <&pmcx0102_d_e0_temp_alarm>; >> + >> + trips { >> + trip0 { >> + temperature = <95000>; >> + hysteresis = <0>; >> + type = "passive"; >> + }; >> + >> + trip1 { >> + temperature = <115000>; >> + hysteresis = <0>; >> + type = "critical"; >> + }; >> + }; >> + }; >> + >> + pmcx0102-c1-thermal { >> + polling-delay-passive = <100>; >> + thermal-sensors = <&pmcx0102_c_e1_temp_alarm>; >> + >> + trips { >> + trip0 { >> + temperature = <95000>; >> + hysteresis = <0>; >> + type = "passive"; >> + }; >> + >> + trip1 { >> + temperature = <115000>; >> + hysteresis = <0>; >> + type = "critical"; >> + }; >> + }; >> + }; >> + >> + pmcx0102-d1-thermal { >> + polling-delay-passive = <100>; >> + thermal-sensors = <&pmcx0102_d_e1_temp_alarm>; >> + >> + trips { >> + trip0 { >> + temperature = <95000>; >> + hysteresis = <0>; >> + type = "passive"; >> + }; >> + >> + trip1 { >> + temperature = <115000>; >> + hysteresis = <0>; >> + type = "critical"; >> + }; >> + }; >> + }; >> + >> + pmh0110-f0-thermal { >> + polling-delay-passive = <100>; >> + thermal-sensors = <&pmh0110_f_e0_temp_alarm>; >> + >> + trips { >> + trip0 { >> + temperature = <95000>; >> + hysteresis = <0>; >> + type = "passive"; >> + }; >> + >> + trip1 { >> + temperature = <115000>; >> + hysteresis = <0>; >> + type = "critical"; >> + }; >> + }; >> + }; >> + >> + pmh0110-h0-thermal { >> + polling-delay-passive = <100>; >> + thermal-sensors = <&pmh0110_h_e0_temp_alarm>; >> + >> + trips { >> + trip0 { >> + temperature = <95000>; >> + hysteresis = <0>; >> + type = "passive"; >> + }; >> + >> + trip1 { >> + temperature = <115000>; >> + hysteresis = <0>; >> + type = "critical"; >> + }; >> + }; >> + }; >> + >> + pmh0110-f1-thermal { >> + polling-delay-passive = <100>; >> + thermal-sensors = <&pmh0110_f_e1_temp_alarm>; >> + >> + trips { >> + trip0 { >> + temperature = <95000>; >> + hysteresis = <0>; >> + type = "passive"; >> + }; >> + >> + trip1 { >> + temperature = <115000>; >> + hysteresis = <0>; >> + type = "critical"; >> + }; >> + }; >> + }; >> + >> + pmh0104-i0-thermal { >> + polling-delay-passive = <100>; >> + thermal-sensors = <&pmh0104_i_e0_temp_alarm>; >> + >> + trips { >> + trip0 { >> + temperature = <95000>; >> + hysteresis = <0>; >> + type = "passive"; >> + }; >> + >> + trip1 { >> + temperature = <115000>; >> + hysteresis = <0>; >> + type = "critical"; >> + }; >> + }; >> + }; >> + >> + pmh0104-j0-thermal { >> + polling-delay-passive = <100>; >> + thermal-sensors = <&pmh0104_j_e0_temp_alarm>; >> + >> + trips { >> + trip0 { >> + temperature = <95000>; >> + hysteresis = <0>; >> + type = "passive"; >> + }; >> + >> + trip1 { >> + temperature = <115000>; >> + hysteresis = <0>; >> + type = "critical"; >> + }; >> + }; >> + }; >> + >> + pmh0104-l1-thermal { >> + polling-delay-passive = <100>; >> + thermal-sensors = <&pmh0104_l_e1_temp_alarm>; >> + >> + trips { >> + trip0 { >> + temperature = <95000>; >> + hysteresis = <0>; >> + type = "passive"; >> + }; >> + >> + trip1 { >> + temperature = <115000>; >> + hysteresis = <0>; >> + type = "critical"; >> + }; >> + }; >> + }; >> + }; >> +}; >