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Wed, 04 Nov 2026 04:31:24 -0800 (PST) Received: from [10.217.219.98] ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-3b07c2ab1cdsm9423184a91.0.2026.11.04.04.31.17 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 04 Nov 2026 04:31:23 -0800 (PST) Message-ID: Date: Wed, 4 Nov 2026 18:01:15 +0530 X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v7 1/3] dt-bindings: i3c: Add support for Qualcomm I3C controller To: alexandre.belloni@bootlin.com, Frank.Li@nxp.com, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, shubhrajyoti.datta@amd.com, shubhamsanjay.patil@amd.com, adrian.hunter@intel.com, manikanta.guntupalli@amd.com, linux-i3c@lists.infradead.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, jarkko.nikula@linux.intel.com, wsa+renesas@sang-engineering.com, alok.a.tiwari@oracle.com Cc: konrad.dybcio@oss.qualcomm.com, andersson@kernel.org, jyothi.seerapu@oss.qualcomm.com, viken.dadhaniya@oss.qualcomm.com, aniket.randive@oss.qualcomm.com, praveen.talari@oss.qualcomm.com References: <20261104111610.3739095-1-mukesh.savaliya@oss.qualcomm.com> Content-Language: en-US From: Mukesh Savaliya In-Reply-To: <20261104111610.3739095-1-mukesh.savaliya@oss.qualcomm.com> Content-Type: text/plain; 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I missed including the cover letter with this series. Please ignore this series without the cover letter. I have resent the complete series with the cover letter included. Sorry for the inconvenience. On 11/4/2026 4:46 PM, Mukesh Kumar Savaliya wrote: > Add device tree bindings for the Qualcomm GENI-based I3C controller. > > The controller supports I3C SDR transfers in mixed-bus mode with both I2C > and I3C target devices present on the same bus. The binding describes the > I3C controller instance along with its associated In-Band Interrupt (IBI) > controller used for handling I3C target IBI events. > > Document the required resources, interrupts, clocks, and dependencies > needed to represent the hardware in device tree. > > Signed-off-by: Mukesh Kumar Savaliya > --- > .../bindings/i3c/qcom,geni-i3c.yaml | 115 ++++++++++++++++++ > 1 file changed, 115 insertions(+) > create mode 100644 Documentation/devicetree/bindings/i3c/qcom,geni-i3c.yaml > > diff --git a/Documentation/devicetree/bindings/i3c/qcom,geni-i3c.yaml b/Documentation/devicetree/bindings/i3c/qcom,geni-i3c.yaml > new file mode 100644 > index 000000000000..bab89aeee23f > --- /dev/null > +++ b/Documentation/devicetree/bindings/i3c/qcom,geni-i3c.yaml > @@ -0,0 +1,115 @@ > +# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/i3c/qcom,geni-i3c.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Qualcomm Geni based QUP I3C Controller > + > +maintainers: > + - Mukesh Kumar Savaliya > + > +description: > + Qualcomm GENI-based I3C controller implementing an MIPI I3C bus master. > + The controller supports SDR transfers in mixed bus mode with both I2C and > + I3C target devices present on the same bus. > + > + The controller consists of a GENI Serial Engine (SE) responsible for I3C > + bus transactions and an associated dedicated IBI controller(IBI_C) block > + used for Hot-Join, In-Band Interrupt (IBI) handling and management of GPII > + resources associated with the I3C controller. > + > + I3C controller nodes must be child nodes of a GENI-based Qualcomm Universal > + Peripheral(QUP) wrapper. Refer to the GENI QUP wrapper binding described in > + Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.yaml. > + > +allOf: > + - $ref: i3c.yaml# > + - $ref: /schemas/soc/qcom/qcom,se-common-props.yaml# > + > +properties: > + compatible: > + const: qcom,geni-i3c > + > + reg: > + items: > + - description: SE (Serial Engine) register address space > + - description: IBI controller (IBI_C) register address space > + > + clocks: > + maxItems: 1 > + > + clock-names: > + const: se > + > + interrupts: > + items: > + - description: Core Serial Engine (SE) IRQ > + - description: IBI controller (IBI_C) manager IRQ > + - description: IBI controller (IBI_C) GPII IRQ > + > + interconnects: > + minItems: 2 > + maxItems: 3 > + > + interconnect-names: > + minItems: 2 > + items: > + - const: qup-core > + - const: qup-config > + - const: qup-memory > + > + pinctrl-names: > + minItems: 1 > + items: > + - const: default > + - const: sleep > + > + dmas: > + maxItems: 2 > + > + dma-names: > + items: > + - const: tx > + - const: rx > + > +required: > + - compatible > + - reg > + - clocks > + - clock-names > + - interrupts > + - interconnects > + - interconnect-names > + - pinctrl-0 > + - pinctrl-1 > + - pinctrl-names > + > +unevaluatedProperties: false > + > +examples: > + - | > + #include > + #include > + #include > + > + i3c@884000 { > + compatible = "qcom,geni-i3c"; > + reg = <0x00884000 0x4000>, > + <0x008c0000 0x10000>; > + clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; > + clock-names = "se"; > + interrupts = , > + , > + ; > + interconnects = <&clk_virt MASTER_QUP_CORE_2 &clk_virt SLAVE_QUP_CORE_2>, > + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_2>, > + <&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>; > + interconnect-names = "qup-core", "qup-config", "qup-memory"; > + pinctrl-0 = <&qup_i3c1_data_clk>; > + pinctrl-1 = <&qup_i3c1_data_clk_sleep>; > + pinctrl-names = "default", "sleep"; > + #address-cells = <3>; > + #size-cells = <0>; > + }; > +...