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[86.188.11.239]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-483bfb9d9c6sm67853935e9.14.2026.02.27.14.04.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 27 Feb 2026 14:04:56 -0800 (PST) Message-ID: Subject: Re: [PATCH v8 10/18] arm64: dts: qcom: x1e80100: Add MIPI CSI PHY nodes From: Christopher Obbard To: Bryan O'Donoghue , Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Robert Foss , Todor Tomov , Mauro Carvalho Chehab , Konrad Dybcio , Vladimir Zapolskiy , Bryan O'Donoghue Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-media@vger.kernel.org, Krzysztof Kozlowski Date: Fri, 27 Feb 2026 22:04:55 +0000 In-Reply-To: <20260225-b4-linux-next-25-03-13-dtsi-x1e80100-camss-v8-10-95517393bcb2@linaro.org> References: <20260225-b4-linux-next-25-03-13-dtsi-x1e80100-camss-v8-0-95517393bcb2@linaro.org> <20260225-b4-linux-next-25-03-13-dtsi-x1e80100-camss-v8-10-95517393bcb2@linaro.org> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable User-Agent: Evolution 3.56.2-8 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Hi Bryan, On Wed, 2026-02-25 at 15:11 +0000, Bryan O'Donoghue wrote: > Add csiphy nodes for >=20 > - csiphy0 > - csiphy1 > - csiphy2 > - csiphy4 >=20 > The irregular naming of the PHYs comes directly from the hardware which f= or > whatever reason skipped csiphy3. >=20 > Separating the nodes from CAMSS as we have done with the sensor I2C bus a= ka > the CCI interface is justified since the CSIPHYs have their own pinouts a= nd > voltage rails. >=20 > Signed-off-by: Bryan O'Donoghue > --- Reviewed-by: Christopher Obbard Tested-by: Christopher Obbard > arch/arm64/boot/dts/qcom/hamoa.dtsi | 115 ++++++++++++++++++++++++++++++= ++++++ > 1 file changed, 115 insertions(+) >=20 > diff --git a/arch/arm64/boot/dts/qcom/hamoa.dtsi b/arch/arm64/boot/dts/qc= om/hamoa.dtsi > index 38f9da6ad9ca5..9c5ebe1b48ecd 100644 > --- a/arch/arm64/boot/dts/qcom/hamoa.dtsi > +++ b/arch/arm64/boot/dts/qcom/hamoa.dtsi > @@ -707,6 +707,25 @@ smem_mem: smem@ffe00000 { > }; > }; > =20 > + csiphy_opp_table: opp-table-csiphy { > + compatible =3D "operating-points-v2"; > + > + opp-300000000 { > + opp-hz =3D /bits/ 64 <300000000>; > + required-opps =3D <&rpmhpd_opp_low_svs_d1>; > + }; > + > + opp-400000000 { > + opp-hz =3D /bits/ 64 <400000000>; > + required-opps =3D <&rpmhpd_opp_low_svs>; > + }; > + > + opp-480000000 { > + opp-hz =3D /bits/ 64 <480000000>; > + required-opps =3D <&rpmhpd_opp_low_svs>; > + }; > + }; > + > qup_opp_table_100mhz: opp-table-qup100mhz { > compatible =3D "operating-points-v2"; > =20 > @@ -5543,6 +5562,102 @@ cci1_i2c1: i2c-bus@1 { > }; > }; > =20 > + csiphy0: csiphy@ace4000 { > + compatible =3D "qcom,x1e80100-csi2-phy"; > + reg =3D <0 0x0ace4000 0 0x2000>; > + > + clocks =3D <&camcc CAM_CC_CSIPHY0_CLK>, > + <&camcc CAM_CC_CSI0PHYTIMER_CLK>, > + <&camcc CAM_CC_CAMNOC_AXI_RT_CLK>, > + <&camcc CAM_CC_CPAS_AHB_CLK>; > + clock-names =3D "csiphy", > + "csiphy_timer", > + "camnoc_axi", > + "cpas_ahb"; > + > + operating-points-v2 =3D <&csiphy_opp_table>; > + > + interrupts =3D ; > + > + power-domains =3D <&camcc CAM_CC_TITAN_TOP_GDSC>; > + > + #phy-cells =3D <1>; > + > + status =3D "disabled"; > + }; > + > + csiphy1: csiphy@ace6000 { > + compatible =3D "qcom,x1e80100-csi2-phy"; > + reg =3D <0 0x0ace6000 0 0x2000>; > + > + clocks =3D <&camcc CAM_CC_CSIPHY1_CLK>, > + <&camcc CAM_CC_CSI1PHYTIMER_CLK>, > + <&camcc CAM_CC_CAMNOC_AXI_RT_CLK>, > + <&camcc CAM_CC_CPAS_AHB_CLK>; > + clock-names =3D "csiphy", > + "csiphy_timer", > + "camnoc_axi", > + "cpas_ahb"; > + > + operating-points-v2 =3D <&csiphy_opp_table>; > + > + interrupts =3D ; > + > + power-domains =3D <&camcc CAM_CC_TITAN_TOP_GDSC>; > + > + #phy-cells =3D <1>; > + > + status =3D "disabled"; > + }; > + > + csiphy2: csiphy@ace8000 { > + compatible =3D "qcom,x1e80100-csi2-phy"; > + reg =3D <0 0x0ace8000 0 0x2000>; > + > + clocks =3D <&camcc CAM_CC_CSIPHY2_CLK>, > + <&camcc CAM_CC_CSI2PHYTIMER_CLK>, > + <&camcc CAM_CC_CAMNOC_AXI_RT_CLK>, > + <&camcc CAM_CC_CPAS_AHB_CLK>; > + clock-names =3D "csiphy", > + "csiphy_timer", > + "camnoc_axi", > + "cpas_ahb"; > + > + operating-points-v2 =3D <&csiphy_opp_table>; > + > + interrupts =3D ; > + > + power-domains =3D <&camcc CAM_CC_TITAN_TOP_GDSC>; > + > + #phy-cells =3D <1>; > + > + status =3D "disabled"; > + }; > + > + csiphy4: csiphy@acec000 { > + compatible =3D "qcom,x1e80100-csi2-phy"; > + reg =3D <0 0x0acec000 0 0x2000>; > + > + clocks =3D <&camcc CAM_CC_CSIPHY4_CLK>, > + <&camcc CAM_CC_CSI4PHYTIMER_CLK>, > + <&camcc CAM_CC_CAMNOC_AXI_RT_CLK>, > + <&camcc CAM_CC_CPAS_AHB_CLK>; > + clock-names =3D "csiphy", > + "csiphy_timer", > + "camnoc_axi", > + "cpas_ahb"; > + > + operating-points-v2 =3D <&csiphy_opp_table>; > + > + interrupts =3D ; > + > + power-domains =3D <&camcc CAM_CC_TITAN_TOP_GDSC>; > + > + #phy-cells =3D <1>; > + > + status =3D "disabled"; > + }; > + > camcc: clock-controller@ade0000 { > compatible =3D "qcom,x1e80100-camcc"; > reg =3D <0 0x0ade0000 0 0x20000>;