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Thu, 05 Feb 2026 06:39:30 -0800 (PST) Received: from [192.168.88.32] ([216.128.11.114]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-4361805813asm14040331f8f.27.2026.02.05.06.39.29 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 05 Feb 2026 06:39:30 -0800 (PST) Message-ID: Date: Thu, 5 Feb 2026 15:39:28 +0100 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH V2 net-next] net: stmmac: dwmac-loongson: Set clk_csr_i to 100-150MHz To: Huacai Chen , Huacai Chen , Andrew Lunn , "David S . Miller" , Eric Dumazet , Jakub Kicinski Cc: Yanteng Si , Alexandre Torgue , Jose Abreu , Serge Semin , loongarch@lists.linux.dev, netdev@vger.kernel.org, linux-kernel@vger.kernel.org, stable@vger.kernel.org, Hongliang Wang References: <20260203062901.2158236-1-chenhuacai@loongson.cn> Content-Language: en-US From: Paolo Abeni In-Reply-To: <20260203062901.2158236-1-chenhuacai@loongson.cn> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit On 2/3/26 7:29 AM, Huacai Chen wrote: > Current clk_csr_i setting of Loongson STMMAC (including LS7A1000/2000 > and LS2K1000/2000/3000) are copy & paste from other drivers. In fact, > Loongson STMMAC use 125MHz clocks and need 62 freq division to within > 2.5MHz, meeting most PHY MDC requirement. So fix by setting clk_csr_i > to 100-150MHz, otherwise some PHYs may link fail. > > Cc: stable@vger.kernel.org > Fixes: 30bba69d7db40e7 ("stmmac: pci: Add dwmac support for Loongson") > Signed-off-by: Hongliang Wang > Signed-off-by: Huacai Chen This should go via the 'net' tree right? /P