From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932554Ab3KLV6x (ORCPT ); Tue, 12 Nov 2013 16:58:53 -0500 Received: from am1ehsobe001.messaging.microsoft.com ([213.199.154.204]:2366 "EHLO am1outboundpool.messaging.microsoft.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932515Ab3KLV6c convert rfc822-to-8bit (ORCPT ); Tue, 12 Nov 2013 16:58:32 -0500 X-Forefront-Antispam-Report: CIP:149.199.60.83;KIP:(null);UIP:(null);IPV:NLI;H:xsj-gw1;RD:unknown-60-83.xilinx.com;EFVD:NLI X-SpamScore: -2 X-BigFish: VPS-2(zzbb2dI98dIc89bh1432Izz1f42h2148h208ch1ee6h1de0h1fdah2073h2149h2146h1202h1e76h1d1ah1d2ah1fc6hzz1de098h8275bh1de097hz2fh95h839h93fhd24hf0ah119dh1288h12a5h12a9h12bdh137ah13b6h1441h14ddh1504h1537h153bh162dh1631h1758h18e1h1946h19b5h1b0ah224fh1d0ch1d2eh1d3fh1dfeh1dffh1e1dh1fe8h1ff5h209eh2216h906i1155h192ch) Date: Tue, 12 Nov 2013 13:58:17 -0800 From: =?utf-8?B?U8O2cmVu?= Brinkmann To: Sudeep KarkadaNagesha , Peter Crosthwaite CC: "rob.herring@calxeda.com" , Pawel Moll , Mark Rutland , Stephen Warren , Ian Campbell , Russell King , Michal Simek , Daniel Lezcano , Thomas Gleixner , "devicetree@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" Subject: Re: [PATCH 2/7] arm: dt: zynq: Add 'cpus' node References: <1383945677-29674-1-git-send-email-soren.brinkmann@xilinx.com> <1383945677-29674-3-git-send-email-soren.brinkmann@xilinx.com> <528128A8.9060400@arm.com> <91c27955-2d9f-4e85-8d9e-b8a178b76cdb@CO9EHSMHS026.ehs.local> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Disposition: inline In-Reply-To: <91c27955-2d9f-4e85-8d9e-b8a178b76cdb@CO9EHSMHS026.ehs.local> User-Agent: Mutt/1.5.21 (2010-09-15) X-RCIS-Action: ALLOW Message-ID: Content-Transfer-Encoding: 8BIT X-OriginatorOrg: xilinx.com X-FOPE-CONNECTOR: Id%0$Dn%*$RO%0$TLS%0$FQDN%$TlsDn% Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, Nov 12, 2013 at 10:06:05AM -0800, Sören Brinkmann wrote: > On Mon, Nov 11, 2013 at 06:57:44PM +0000, Sudeep KarkadaNagesha wrote: > > On 08/11/13 21:21, Soren Brinkmann wrote: > > > Add a 'cpus' node to describe the CPU cores of Zynq. > > > > > > Signed-off-by: Soren Brinkmann > > > Acked-by: Peter Crosthwaite > > > --- > > > arch/arm/boot/dts/zynq-7000.dtsi | 27 +++++++++++++++++++++++++++ > > > 1 file changed, 27 insertions(+) > > > > > > diff --git a/arch/arm/boot/dts/zynq-7000.dtsi b/arch/arm/boot/dts/zynq-7000.dtsi > > > index 27ebc1ba9671..37fc04525142 100644 > > > --- a/arch/arm/boot/dts/zynq-7000.dtsi > > > +++ b/arch/arm/boot/dts/zynq-7000.dtsi > > > @@ -15,6 +15,33 @@ > > > / { > > > compatible = "xlnx,zynq-7000"; > > > > > > + cpus { > > > + #address-cells = <1>; > > > + #size-cells = <0>; > > > + > > > + cpu@0 { > > > + compatible = "arm,cortex-a9"; > > > + device_type = "cpu"; > > > + reg = <0>; > > > + clocks = <&clkc 3>; > > > + i-cache-size = <0x8000>; > > > + i-cache-line-size = <0x20>; > > > + d-cache-size = <0x8000>; > > > + d-cache-line-size = <0x20>; > > > > These cache properties can be identified through CCSIDR(Cache Size ID Registers) > > on ARMv7 Cortex implementations. It's better not to have these in DT if they can > > be identified runtime. > Sounds good to me. I'll go ahead an remove them. BTW: Documentation/devicetree/booting-without-of.txt lists those properties at least as recommended. That should probably be updated. Sören