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Mon, 25 May 2026 03:38:26 -0700 (PDT) X-Received: by 2002:a05:6a21:a45:b0:3aa:3fbf:d0a3 with SMTP id adf61e73a8af0-3b328fb7b6fmr15349682637.47.1779705506118; Mon, 25 May 2026 03:38:26 -0700 (PDT) Received: from [10.217.216.23] ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-84164affc22sm9242136b3a.21.2026.05.25.03.38.19 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 25 May 2026 03:38:25 -0700 (PDT) Message-ID: Date: Mon, 25 May 2026 16:08:18 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v8 2/9] clk: qcom: gcc-msm8939: mark Venus core GDSCs as hardware controlled To: Erikas Bitovtas , Bryan O'Donoghue , Vikash Garodia , Dikshita Agarwal , Mauro Carvalho Chehab , Rob Herring , Krzysztof Kozlowski , Conor Dooley , =?UTF-8?Q?Andr=C3=A9_Apitzsch?= , Bjorn Andersson , Konrad Dybcio , Michael Turquette , Stephen Boyd , Brian Masney Cc: linux-media@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org References: <20260519-msm8939-venus-rfc-v8-0-542ec7557ebc@gmail.com> <20260519-msm8939-venus-rfc-v8-2-542ec7557ebc@gmail.com> <608dc53d-17a8-4230-9ebb-48a94bf03675@kernel.org> <6ae3a89c-f205-45c5-87c0-5550f78502d6@oss.qualcomm.com> <01f9a303-846a-4048-8115-c94b9b78078a@gmail.com> Content-Language: en-US From: Taniya Das In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNTI1MDEwOCBTYWx0ZWRfX1JZAlAz7pgq3 t/BEJelGpz1w7qCQGvwXdLvuPvvWkNk8XQBGHDK3a5GHCVpkX7Vz41z8TYKaGCgpaQZ+hYKMx1P PpEZeGGbc0HYtyPaS09fbPf3294BrM3XhsM079fnzD4QiRYsHLBEbOoBeWMgPOzW49eArrpw6Mr NXxOcV8nRJhbNALt0GXxC9/4f8eJ9L3HFXAPeix+Wp7YJg27+V9MMk+gI2tFRV16futydqH4Ax8 BAcqi1zQd2c3FJd123S1AA6xnwPla/ApAchxCxoY+qYN36CgxQHP3NOYeqOdGVyKwj/8BBmDQDB ShHFl6brwQH7kZAgsw7lwOjRFIp2eAjM4a2cKQxHGqgYlNuj/3W98FdzRw3Lok7zWvP96IjYah+ PSZLqWNokFztA1wg20ZpQ5hIURg9GJ/beytif4Y+NLl88M9UjPE/2NyPdvQ/zjgNTVCpe+PqQKA /FXxRpRsCjy6zeehlRQ== X-Proofpoint-ORIG-GUID: kKwLVAhDFsA7WVAzgZdHvBb1pkFdq_Nt X-Authority-Analysis: v=2.4 cv=cN3QdFeN c=1 sm=1 tr=0 ts=6a1426a3 cx=c_pps a=oF/VQ+ItUULfLr/lQ2/icg==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=NGcC8JguVDcA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=rJkE3RaqiGZ5pbrm-msn:22 a=plRfSYbjXIbEfgUgcesA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=3WC7DwWrALyhR5TkjVHa:22 X-Proofpoint-GUID: kKwLVAhDFsA7WVAzgZdHvBb1pkFdq_Nt X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-05-25_03,2026-05-18_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 suspectscore=0 adultscore=0 priorityscore=1501 phishscore=0 spamscore=0 bulkscore=0 lowpriorityscore=0 impostorscore=0 clxscore=1015 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2605130000 definitions=main-2605250108 On 5/25/2026 3:26 PM, Erikas Bitovtas wrote: > > > On 5/25/26 8:51 AM, Taniya Das wrote: >> >> >> On 5/22/2026 4:18 PM, Erikas Bitovtas wrote: >>>>>>   static struct clk_branch gcc_venus0_core0_vcodec0_clk = { >>>>>>       .halt_reg = 0x4c02c, >>>>>> +    .halt_check = BRANCH_HALT_SKIP, >>>> please use .halt_check = BRANCH_HALT >>>> >>> If I do that, the clock fails to power on on boot. >>> [ 20.324488] ------------[ cut here ]------------ >>> [ 20.324520] gcc_venus0_core0_vcodec0_clk status stuck at 'off' >>> [ 20.324663] WARNING: drivers/clk/qcom/clk-branch.c:88 at >> >> >> I am hoping the Venus driver has enabled the GDSC before requesting the >> clock enable. >> > It does. From 3/9: > +static int vcodec_domains_enable(struct venus_core *core) > +{ > + const struct venus_resources *res = core->res; > + struct device *pd_dev; > + int i = 0, ret; > + > + if (!res->vcodec_pmdomains) > + return 0; > + > + for (; i < res->vcodec_pmdomains_num; i++) { > + pd_dev = core->pmdomains->pd_devs[i]; > + ret = pm_runtime_resume_and_get(pd_dev); > + if (ret) > + goto err; > + > + ret = dev_pm_genpd_set_hwmode(pd_dev, true); > + if (ret && ret != -EOPNOTSUPP) { > + pm_runtime_put_sync(pd_dev); > + goto err; > + } > + } > > static void core_put_v1(struct venus_core *core) > @@ -320,11 +410,35 @@ static int core_power_v1(struct venus_core *core, > int on) > { > int ret = 0; > > - if (on == POWER_ON) > + if (on == POWER_ON) { > + ret = vcodec_domains_enable(core); > + if (ret) > + return ret; > + > ret = core_clks_enable(core); > - else > + if (ret) > + goto fail_pmdomains; > + > + if (!core->res->vcodec_pmdomains) > + return 0; > + > + ret = vcodec_clks_enable(core, core->vcodec_clks); > + if (ret) > + goto fail_core_clks; > + Please check this sequence is taken care or not Power-up/Boot-up 1. Enable GDSC 2. Enable clocks 3. Request GDSC to HW control via 'dev_pm_genpd_set_hwmode', true Power-Down 4. Request GDSC to SW control via 'dev_pm_genpd_set_hwmode', false 5. Disable clocks 6. Disable GDSC -- Thanks, Taniya Das