From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 249CF3F65E7; Wed, 19 Aug 2026 14:19:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787149200; cv=none; b=GzZEF7ttUo+J4aHqoYXotYbssM2pLDF0SGDEBlzBLCLU9AgvS3D4F5fI4q/pnLv9qBMctjP339RzQYVTWPeoHa1NLKImT5NJFTVJTrCATtct7hM9JfOGpfuzH7gBp1ZnWHAEVdH8tU1AvUK+QbAGM2Bv4ET3k3Ewadd//J3f1xI= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787149200; c=relaxed/simple; bh=Qntx+DICTwYYOR7kmGD1FqDralBSYil8UX+NQG0zbs0=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=G3io6rNsLvpRDO6RR/Hv3dJYdANvbsQMDXC/nNeON3E8ujSjxvIZEujpxHgJo2EJ9+IW5BQYvNdz6DCR6kMEGo6AeOW9mMtVioA+73HbCjj7WTe3AsGDATAA5wglDtdVKsfjIw2qhe0nkpH3TtiWGXgwp46NY6eDTKDlKFeUoyg= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=A5WSjRl9; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="A5WSjRl9" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 507FC1F00A3A; Wed, 19 Aug 2026 14:19:47 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1787149198; bh=CSiaMruoRBtV9sjxtyni0VM6A7qy7GPlv2ijASfOuMw=; h=Date:Subject:To:Cc:References:From:In-Reply-To; b=A5WSjRl9XMcme2a0xUSy5MvwdhbuLcF8R1/D8Kkekyg3WyPraeUcxcoUKNfjsNTBV JeqC1r+yzIwHiFTmbv38fs01SRXY+685er1w3yBpMrtJYAPRix+YidLCBFTf8pBnXn E1V5xvwSlLs4rVNpwpawlpJd7CAV5DbGGuGWCeLF3N4cOGCP8gZzJFud9U0iKLmTWW 0xcZ+OETeZwsfD87wWZG+SzmkXT/Rqxzyz9LoyTc759In7U4xG3avGeL3WWEJxSBVM GEGP2x4FB8LFfvfhwdiMVcaBYVCv9Zb5yhml6f5RXF+yMMglUXt4qGlIp1wh/Nj4Zc gwasf2BCLJERQ== Message-ID: Date: Wed, 19 Aug 2026 16:19:45 +0200 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 00/15] accel/qda: Qualcomm DSP Accelerator driver To: Ekansh Gupta , Oded Gabbay , Jonathan Corbet , Shuah Khan , Randy Dunlap , Nathan Chancellor , Nick Desaulniers , Bill Wendling , Justin Stitt , "Joerg Roedel (AMD)" , Will Deacon , Robin Murphy , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Sumit Semwal , =?UTF-8?Q?Christian_K=C3=B6nig?= Cc: Bharath Kumar , Chenna Kesava Raju , srinivas.kandagatla@oss.qualcomm.com, dmitry.baryshkov@oss.qualcomm.com, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-doc@vger.kernel.org, linux-arm-msm@vger.kernel.org, llvm@lists.linux.dev, iommu@lists.linux.dev, linux-media@vger.kernel.org, linaro-mm-sig@lists.linaro.org References: <20260817-qda-v2-v2-0-69a02e9090d4@oss.qualcomm.com> <3322b42b-3755-45ec-ad55-345125f0d488@kernel.org> <3b235b4c-0c1c-400a-b081-0df881cab06d@kernel.org> <4000bb8b-20a7-4ab0-9330-49395022e78f@oss.qualcomm.com> From: Krzysztof Kozlowski Content-Language: en-US Autocrypt: addr=krzk@kernel.org; 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charset=UTF-8 Content-Transfer-Encoding: 8bit On 19/08/2026 15:32, Ekansh Gupta wrote: > On 19-08-2026 00:51, Krzysztof Kozlowski wrote: >> On 18/08/2026 21:13, Krzysztof Kozlowski wrote: >>> On 17/08/2026 06:47, Ekansh Gupta wrote: >>>> This patch series introduces the Qualcomm DSP Accelerator (QDA) driver, >>>> a DRM-based accelerator driver for Qualcomm DSPs. The driver provides a >>>> standardized interface for offloading computational tasks to DSPs found >>>> on Qualcomm SoCs, supporting all DSP domains. >>>> >>>> The QDA driver implements the FastRPC protocol over the DRM accel >>>> subsystem. It uses the same device-tree node structure as the existing >>>> fastrpc driver in drivers/misc/. The approach for binding the QDA driver >>>> to device-tree nodes while coexisting with the fastrpc driver is an open >>>> item described below. >>> >>> No. Grow/replace/improve existing driver instead of coming with a duplicate. >>> >>> That's a standard upstream requirement, basically given on every >>> upstreaming guide. >>> >>> Please watch old talk from Greg - "I Don’t Want Your Code!". >>> >>>> >>>> v1: https://lore.kernel.org/all/20260519-qda-series-v1-0-b2d984c297f8@oss.qualcomm.com/ >>>> RFC: https://lore.kernel.org/dri-devel/20260224-qda-firstpost-v1-0-fe46a9c1a046@oss.qualcomm.com/T/ >>>> >>>> Changes since v1 >>>> ================ >>>> >>>> The v1 review raised two architectural objections and one correctness >>>> issue; all three are resolved in v2: >>>> >>>> * Christian König (dma-buf maintainer) pointed out that the imported- >>>> buffer path silently assumed the IOMMU maps every buffer as a single >>>> contiguous range, which is not guaranteed. v2 walks the scatterlist >>>> and cleanly rejects non-contiguous imports; contiguous imports (e.g. >>>> CMA DMA-buf heap) are accepted. (patch 11) >>>> >>>> * Dmitry Baryshkov objected to three different buffer-passing formats >>>> in the invoke IOCTL (DMA-BUF fd, direct/inline, DMA handle). v2 >>>> passes only GEM handles; userspace imports any fd to a GEM handle >>>> with DRM_IOCTL_PRIME_FD_TO_HANDLE before invoking. Packing and >>>> overlap handling are left to userspace. (patch 12) >>>> >>>> * The memory manager (patch 07) used a fixed 16-entry array without >>>> justification and leaked the device descriptor on teardown. v2 >>>> allocates the array from the DT context-bank count (as Dmitry >>>> suggested) and frees it correctly. >>>> >>>> User-space staging branch >>>> ========================= >>>> https://github.com/qualcomm/fastrpc/tree/accel/staging >>>> >>>> Key Features >>>> ============ >>>> >>>> * Standard DRM accelerator interface via /dev/accel/accelN >>>> * GEM-based buffer management with DMA-BUF import (PRIME) >>>> * IOMMU-based memory isolation using per-process context banks >>>> * FastRPC protocol implementation for DSP communication >>>> * RPMsg transport layer for reliable message passing >>>> * Support for all DSP domains (ADSP, CDSP, SDSP, GDSP) >>>> * DRM IOCTL interface for DSP session management, buffer allocation, >>>> and remote procedure invocation >>>> >>>> Architecture >>>> ============ >>>> >>>> 1. DRM Accelerator Framework Integration >>>> The driver registers as a DRM accel device, exposing a standard >>>> /dev/accel/accelN character device node. This provides established >>>> DRM infrastructure for device management, file operations, and >>>> IOCTL dispatch. >>>> >>>> 2. Memory Management >>>> Buffers are managed as GEM objects with PRIME support for DMA-BUF >>>> import. This enables buffer sharing with other DRM drivers (GPU, >>>> camera, video) using standard kernel mechanisms. Only contiguous >>>> imports are accepted; the driver verifies contiguity at import time >>>> rather than assuming it. >>>> >>>> 3. IOMMU Context Bank Management >>>> IOMMU context banks (CBs) are represented as proper struct device >>>> instances on a custom virtual bus (qda-compute-cb). Each CB device >>>> is registered with the IOMMU subsystem and receives its own IOMMU >>>> domain, enabling per-session address space isolation. The custom >>>> bus was introduced because IOMMU context banks are synthetic >>>> constructs — not real platform devices — and to ensure CB device >>>> lifetime is strictly subordinate to the parent QDA device. >>>> See also: https://lore.kernel.org/all/245d602f-3037-4ae3-9af9-d98f37258aae@oss.qualcomm.com/ >>>> >>>> 4. Memory Manager Architecture >>>> The memory manager maintains a registry of IOMMU devices in an >>>> array sized to the number of context banks described in the device >>>> tree, and coordinates per-process device assignment with reference- >>>> counted lifetime management. The DMA-coherent backend allocates >>>> buffers with SID-prefixed DMA addresses for DSP firmware >>>> compatibility. >>>> >>>> 5. Transport Layer >>>> RPMsg communication is handled in a dedicated transport layer >>>> (qda_rpmsg.c), separate from the core DRM driver logic. >>>> >>>> 6. Code Organization >>>> The driver is organized across multiple files (~4800 lines total): >>>> * qda_drv.c: Core driver and DRM integration >>>> * qda_rpmsg.c: RPMsg transport layer >>>> * qda_cb.c: Context bank device management >>>> * qda_compute_bus.c: Custom virtual bus for CB devices >>>> * qda_gem.c: GEM object management >>>> * qda_prime.c: DMA-BUF import (PRIME) >>>> * qda_memory_manager.c: IOMMU device registry and allocation >>>> * qda_memory_dma.c: DMA-coherent allocation backend >>>> * qda_fastrpc.c: FastRPC protocol implementation >>>> * qda_ioctl.c: IOCTL dispatch >>>> >>>> 7. UAPI Design >>>> The driver exposes DRM-style IOCTLs defined in >>>> include/uapi/drm/qda_accel.h, following DRM UAPI conventions >>>> (__u32/__u64 types, C++ guard, GPL-2.0-only WITH Linux-syscall-note). >>>> Buffer arguments are identified by GEM handles; the driver never >>>> accepts DMA-BUF fds directly in any IOCTL. >>>> >>>> Patch Series Organization >>>> ========================== >>>> >>>> Patch 01: MAINTAINERS entry >>>> Patch 02: Driver documentation (Documentation/accel/qda/) >>>> Patches 03-04: Core driver skeleton and compute bus >>>> Patch 05: iommu: Register qda-compute-cb bus with IOMMU subsystem >>>> Patches 06-07: CB device enumeration and memory manager >>>> Patch 08: QUERY IOCTL and UAPI header >>>> Patches 09-11: GEM buffer management and PRIME import >>>> Patches 12-15: FastRPC protocol (invoke, session create/release, >>>> map/unmap) >>>> >>>> Open Items >>>> =========== >>>> >>>> 1. Device-Tree Compatible String >>>> The QDA driver uses the same device-tree node structure and >>>> properties as the existing fastrpc driver in drivers/misc/. A >>>> mechanism is needed to allow the QDA driver to bind to its device >>>> node independently of the fastrpc driver. >>>> >>>> The intended coexistence model is: platforms that require the >>>> complete fastrpc feature set continue to use "qcom,fastrpc"; new >>>> platforms where QDA's feature set is sufficient use a QDA-specific >>>> compatible string. New feature development is directed toward QDA. >>>> >>>> The options under consideration are: >>>> >>>> a) Add a new "qcom,qda" compatible string to the existing >>>> qcom,fastrpc.yaml binding, since the DT node structure and >>>> properties are identical. >>> No >>> >>>> >>>> b) Introduce a separate qcom,qda.yaml binding that references or >>>> inherits the fastrpc binding properties. >>> >>> No >>> >>>> >>>> Seeking guidance from DT binding maintainers on the preferred >>>> approach. >>> >>> Grow existing driver. You do not get new driver, you do not get new >>> bindings. >>> >> >> And this was already questioned at v1 (the true v1, not v1+1) but you >> ignored the comment. > The discussion were around compat layers in v1 patch (which is not yet > concluded) and on whether this driver is going to be an alternative or a No, you got comment, from Trilok I think, asking what is the plan in respect of existing fastrpc driver. Best regards, Krzysztof