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Instead the upstream > configuration should provide the final user_ctl value that is written to > the USER_CTL register. > > Fix the config so that the PLL is configured correctly. > > Fixes: 9f0532da4226 ("clk: qcom: Add Camera Clock Controller driver for SM7150") > Suggested-by: Taniya Das > Signed-off-by: Luca Weiss > --- > drivers/clk/qcom/camcc-sm7150.c | 6 +----- > 1 file changed, 1 insertion(+), 5 deletions(-) > > diff --git a/drivers/clk/qcom/camcc-sm7150.c b/drivers/clk/qcom/camcc-sm7150.c > index 4a3baf5d8e85..590548cac45b 100644 > --- a/drivers/clk/qcom/camcc-sm7150.c > +++ b/drivers/clk/qcom/camcc-sm7150.c > @@ -139,13 +139,9 @@ static struct clk_fixed_factor camcc_pll1_out_even = { > /* 1920MHz configuration */ > static const struct alpha_pll_config camcc_pll2_config = { > .l = 0x64, > - .post_div_val = 0x3 << 8, > - .post_div_mask = 0x3 << 8, > - .early_output_mask = BIT(3), > - .aux_output_mask = BIT(1), > - .main_output_mask = BIT(0), > .config_ctl_hi_val = 0x400003d6, > .config_ctl_val = 0x20000954, > + .user_ctl_val = 0x0000030b, > }; > > static struct clk_alpha_pll camcc_pll2 = { > Reviewed-by: Taniya Das -- Thanks, Taniya Das