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charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Proofpoint-GUID: KFPO_P6hbXezEtDHB_eqLODfrxl1IEkA X-Authority-Analysis: v=2.4 cv=FZuiV5+6 c=1 sm=1 tr=0 ts=6acdee7d cx=c_pps a=wEP8DlPgTf/vqF+yE6f9lg==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=660iZSQnnn4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yOCtJkima9RkubShWh1s:22 a=EUspDBNiAAAA:8 a=cSAlzBlaUu0bmXACLXkA:9 a=QEXdDO2ut3YA:10 a=bBxd6f-gb0O0v-kibOvt:22 X-Proofpoint-Spam-Info: AW1haW4tMjYxMDEzMDAzNCBTYWx0ZWRfX+Rwjb3XTo59E +nu10R1ZfB2yDlx1h431RvtFrLtUl6n/DYK7h1+DWc4fwVg5dVXM46J6us1yf5u1aej69r4VF4l hIjGDLeBEAmtjge3e3neoLEK42Gk1pc= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYxMDEzMDAzNCBTYWx0ZWRfX7sbkpxL5y0V9 PKJAbT5MykS6mPrMCs5Up7Kpwk5jk5XFVi/MflBWnhm44qiONZE+jYE2iXMSLv2ZBm1nw7d+pII CMXI6myVjcLaRsCPly+GDQ0F+8tZ0FfQM0r1/JW4Xxe/kfMyRnF7XllcFWvZtoGbIrtqgzJLJsG 25/iWDDWc1vuZ1VTI0805IDqTk5p1WKQhypRPGJnbprZtdkfhkzyeK2ubBVTMg7HE7k8DLkT6U5 d25Z3pp9SVj9cnqD8ooMeKwDzozsQC7kYCACjaxUsRQTbskj8QfjyCideVgH59+Q5OIXxCHgplU AXl1hnoYYZ5plM5hgN/xj2q9taEwOXgRhJKi9pbUaBCqnhkuCr7lXHSAnA1f2piEt5qLLKvQEa+ ltMxRClFZVMQLWrDPJtOEYb3COFYOlZJUN2P/g55YzEY/znTmfVByh9YhV9snMBY3D4zf7XTJni VXtRgWl3Qwxz4VJaF+w== X-Proofpoint-ORIG-GUID: KFPO_P6hbXezEtDHB_eqLODfrxl1IEkA X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-10-13_01,2026-10-09_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 lowpriorityscore=0 clxscore=1015 impostorscore=0 adultscore=0 bulkscore=0 spamscore=0 malwarescore=0 phishscore=0 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2610080000 definitions=main-2610130034 On 9/29/2026 10:49 AM, Krishna Kurapati wrote: > During plug-in/plug-out test cases, it is sometimes seen that no events > are generated by the controller and all CSR register reads give "0" and > CSR_Timeout bit gets set indicating that CSR reads/writes are timing out > or timed out. > > The issue comes up on different instnaces of enumeration on different > platforms. On SM8550, the debug log is as follows: > > Prepared a TRB on ep0out and did start transfer to get set > address request from host: > > <...>-7191 [000] D..1. 66.421006: dwc3_gadget_ep_cmd: ep0out: > cmd 'Start Transfer' [406] params 00000000 efffa000 00000000 --> > status: Successful > > <...>-7191 [000] D..1. 66.421196: dwc3_event: event (0000c040): > ep0out: Transfer Complete (sIL) [Setup Phase] > > <...>-7191 [000] D..1. 66.421197: dwc3_ctrl_req: Set > Address(Addr = 01) > > An XFER NRDY is received on ep0in for zero length status phase and > a Start Transfer was done on ep0in with 0-length packet in 2 Stage > status phase: > > <...>-7191 [000] D..1. 66.421249: dwc3_event: event (000020c2): > ep0in: Transfer Not Ready [00000000] (Not Active) [Status Phase] > > <...>-7191 [000] D..1. 66.421266: dwc3_prepare_trb: ep0in: trb > ffffffc00fcfd000 (E0:D0) buf 00000000efffa000 size 0 ctrl 00000c33 > sofn 00000000 (HLcs:SC:status2) > > <...>-7191 [000] D..1. 66.421387: dwc3_gadget_ep_cmd: ep0in: cmd > 'Start Transfer' [406] params 00000000 efffa000 00000000 -->status: > Successful > > A bus reset was then received directly after 500 msec. Software never > got the cmd complete for the start transfer done in status phase. Here > the RAM interface is stuck. So host issues a bus reset as link is > idle for 500 msec: > > <...>-7191 [000] D..1. 66.935603: dwc3_event: event (00000101): > Reset [U0] > > Then software sees that it is in status phase and we issue an ENDXFER > on ep0in and it gets timedout waiting for the CMDACT to go '0': > > <...>-7191 [000] D..1. 66.958249: dwc3_gadget_ep_cmd: ep0in: cmd > 'End Transfer' [10508] params 00000000 00000000 00000000 --> status: > Timed Out > > Upon debug with Synopsys, the root cause is as follows: > > During any transfer, if the data is not successfully transmitted, > then a Done (with failure) handshake is returned, so that the BMU > can re-attempt the same data again by rewinding its data pointers. > > But, if the USB IN is a 0-length payload (which is what is happening > in this case - 2 stage status phase of set_address), then there is no > need to rewind the pointers and the Done (with failure) handshake is > not returned for failure case. This keeps the Request-Done interface > busy till the next Done handshake. The MAC sends the 0-length payload > again when the host requests. If the transmission is successful this > time, the Done (with success) handshake is provided back. Otherwise, > it repeats the same steps again. > > If the cable is disconnected or if the Host aborts the transfer on 3 > consecutive failed attempts, the Request-Done handshake is not > complete. This keeps the interface busy. > > The subsequent RAM access cannot proceed until the above pending > transfer is complete. This results in failure of any access to RAM > address locations. Many of the EndPoint commands need to access the > RAM and they would fail to complete successfully. > > Furthermore when cable removal happens, this would not generate a > disconnect event and the "connected" flag remains true always blockin > suspend. > > Synopsys confirmed that the issue is present on all USB3 devices and > as a workaround, suggested to re-initialize device mode. > > Signed-off-by: Krishna Kurapati Thinh, Can you help provide your review on this patch. Regards, Krishna,