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Thu, 15 Oct 2026 07:07:14 -0700 (PDT) X-Received: by 2002:a05:6820:190b:b0:6f7:3c09:c712 with SMTP id 006d021491bc7-701124b05ebmr74380eaf.18.1792073233568; Thu, 15 Oct 2026 07:07:13 -0700 (PDT) Received: from [192.168.0.195] ([124.123.197.202]) by smtp.gmail.com with ESMTPSA id 46e09a7af769-830385b9cb0sm17852906a34.4.2026.10.15.07.07.04 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 15 Oct 2026 07:07:12 -0700 (PDT) Message-ID: Date: Thu, 15 Oct 2026 19:37:00 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 3/4] clk: qcom: av1ecc-glymur: Add AV1E clock controller driver To: Jagadeesh Kona , Bjorn Andersson , Abel Vesa , Stephen Boyd , Brian Masney , Jerome Brunet , Dmitry Baryshkov , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jagadeesh Kona , Konrad Dybcio Cc: Ajit Pandey , Imran Shaik , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org References: <20261015-glymur-av1ecc-v1-0-448a476d54af@oss.qualcomm.com> <20261015-glymur-av1ecc-v1-3-448a476d54af@oss.qualcomm.com> Content-Language: en-US From: Taniya Das In-Reply-To: <20261015-glymur-av1ecc-v1-3-448a476d54af@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-GUID: dRHegxPxqGmPho5BjmwPdLjzNbNu9Ql9 X-Proofpoint-ORIG-GUID: dRHegxPxqGmPho5BjmwPdLjzNbNu9Ql9 X-Proofpoint-Spam-Info: AW1haW4tMjYxMDE1MDA1NiBTYWx0ZWRfX3mt2kuTtC1eP s/3jo7uQ0zQHDLcbeQEnPzjO9pmioJ4Ptpthusvjn9fi8yEYXBsfEe/JTu+No/kWKS2Ks0/cN8X 0Hvpi44a1WdqM6EcPJNGF9y36zaYQig= X-Authority-Analysis: v=2.4 cv=TbQDJhQh c=1 sm=1 tr=0 ts=6ad0de13 cx=c_pps a=OI0sxtj7PyCX9F1bxD/puw==:117 a=/y/JNeyFYS62MWjl30sOOw==:17 a=IkcTkHD0fZMA:10 a=660iZSQnnn4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=YMgV9FUhrdKAYTUUvYB2:22 a=EUspDBNiAAAA:8 a=fkuVY8nhnkbg9sVdVkgA:9 a=QEXdDO2ut3YA:10 a=Z1Yy7GAxqfX1iEi80vsk:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYxMDE1MDA1NiBTYWx0ZWRfX/m2LUyYwnOJv sYPAOmmr8cGEZxdw2hw3+nk3QvpUexwKVxI3oLbsYu4Al/zQQjAfH6cU80kLzwr1vtOO6FCX9wd H4nE7Mqa6zWY7F+NH6IXPpv+UptcJoTjkPCt2tBXU/yyLTDADtxyVPA7BJQbcjOclbqICn1Kla2 o9a5BES58zQwLU/N2l1ocF9x3dq9BRk8DdHjklcP6cvXuTY32AnkKAuDB63ZvtHeXfsEc7mzk0F GdpY6rmm5U2ePrEEwYXeidPvYRoFsLD0Xz2OHstmnHo7rYsXA+8rcudYpvs98H6kaPTaBGEQkZ3 T5/h15Cqpuf/4g2xipDABXKKdcOblPHIkSNn4PH1clIYwfeTdQoiVn2PmwmaLAnVDvVQ8DPy/c9 RYHL98x0UTqi3qdcurOMz99yZwqGPqmoZtPvub6SdBl1Wuu9wJGAywhu7/SO9kr9jm9v3gpFLEe bjao7pxOQxUPPqOnsUw== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-10-14_01,2026-10-14_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 lowpriorityscore=0 bulkscore=0 priorityscore=1501 spamscore=0 clxscore=1015 impostorscore=0 phishscore=0 malwarescore=0 adultscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2610080000 definitions=main-2610150056 On 10/15/2026 7:05 PM, Jagadeesh Kona wrote: > Add support for the AV1 encoder clock controller (AV1ECC) driver > for clients to be able to request for AV1ECC clocks on Qualcomm > Glymur platform. > > Signed-off-by: Jagadeesh Kona > --- > drivers/clk/qcom/Kconfig | 11 ++ > drivers/clk/qcom/Makefile | 1 + > drivers/clk/qcom/av1ecc-glymur.c | 393 +++++++++++++++++++++++++++++++++++++++ > 3 files changed, 405 insertions(+) > > diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig > index 27d0ab24d50a4ca5587ed8d6085c4d6fcd57eb8c..94f3445f6bd0ecd297d83b5804ff0e4433d48261 100644 > --- a/drivers/clk/qcom/Kconfig > +++ b/drivers/clk/qcom/Kconfig > @@ -69,6 +69,17 @@ config CLK_ELIZA_TCSRCC > Support for the TCSR clock controller on Eliza devices. > Say Y if you want to use peripheral devices such as USB/PCIe/UFS. > > +config CLK_GLYMUR_AV1ECC > + tristate "Glymur AV1E Clock Controller" > + depends on ARM64 || COMPILE_TEST > + select CLK_GLYMUR_GCC > + default m if ARCH_QCOM > + help > + Support for the video AV1 encoder clock controller on > + Qualcomm Technologies, Inc. Glymur devices. > + Say Y if you want to support functionality such as AV1 > + encoding. > + > config CLK_GLYMUR_CAMCC > tristate "Glymur Camera Clock Controller" > depends on ARM64 || COMPILE_TEST > diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile > index 6affb5073f269d18f1b78d6c7f92e14baeade1e5..61d4efb7547146544902dddf52e4853d073d5467 100644 > --- a/drivers/clk/qcom/Makefile > +++ b/drivers/clk/qcom/Makefile > @@ -28,6 +28,7 @@ obj-$(CONFIG_CLK_ELIZA_GPUCC) += gpucc-eliza.o > obj-$(CONFIG_CLK_ELIZA_TCSRCC) += tcsrcc-eliza.o > obj-$(CONFIG_CLK_ELIZA_VIDEOCC) += videocc-eliza.o > obj-$(CONFIG_CLK_GFM_LPASS_SM8250) += lpass-gfm-sm8250.o > +obj-$(CONFIG_CLK_GLYMUR_AV1ECC) += av1ecc-glymur.o > obj-$(CONFIG_CLK_GLYMUR_CAMCC) += camcc-glymur.o > obj-$(CONFIG_CLK_GLYMUR_DISPCC) += dispcc-glymur.o > obj-$(CONFIG_CLK_GLYMUR_EVACC) += evacc-glymur.o > diff --git a/drivers/clk/qcom/av1ecc-glymur.c b/drivers/clk/qcom/av1ecc-glymur.c > new file mode 100644 > index 0000000000000000000000000000000000000000..228e73a1a1357dc9ebe508b9fbcec71326388806 > --- /dev/null > +++ b/drivers/clk/qcom/av1ecc-glymur.c > @@ -0,0 +1,393 @@ > +// SPDX-License-Identifier: GPL-2.0-only > +/* > + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. > + */ > + > +#include > +#include > +#include > +#include > + > +#include > + > +#include "clk-alpha-pll.h" > +#include "clk-branch.h" > +#include "clk-pll.h" > +#include "clk-rcg.h" > +#include "clk-regmap.h" > +#include "clk-regmap-divider.h" > +#include "common.h" > +#include "gdsc.h" > +#include "reset.h" > + > +enum { > + DT_BI_TCXO, > + DT_IFACE, > +}; > + > +enum { > + P_AV1E_CC_PLL0_OUT_EVEN, > + P_AV1E_CC_PLL0_OUT_MAIN, > + P_AV1E_CC_PLL0_OUT_ODD, > + P_BI_TCXO, > +}; > + > +static const struct pll_vco taycan_eko_t_vco[] = { > + { 249600000, 2500000000, 0 }, > +}; > + > +/* 600.0 MHz Configuration */ > +static const struct alpha_pll_config av1e_cc_pll0_config = { > + .l = 0x1f, > + .cal_l = 0x48, > + .alpha = 0x4000, > + .config_ctl_val = 0x25c400e7, > + .config_ctl_hi_val = 0x0a8060e0, > + .config_ctl_hi1_val = 0xf51dea20, > + .user_ctl_val = 0x00000008, > + .user_ctl_hi_val = 0x00000002, > +}; > + > +static struct clk_alpha_pll av1e_cc_pll0 = { > + .offset = 0x0, > + .config = &av1e_cc_pll0_config, > + .vco_table = taycan_eko_t_vco, > + .num_vco = ARRAY_SIZE(taycan_eko_t_vco), > + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_EKO_T], > + .clkr = { > + .hw.init = &(const struct clk_init_data) { > + .name = "av1e_cc_pll0", > + .parent_data = &(const struct clk_parent_data) { > + .index = DT_BI_TCXO, > + }, > + .num_parents = 1, > + .ops = &clk_alpha_pll_taycan_eko_t_ops, > + }, > + }, > +}; > + > +static const struct parent_map av1e_cc_parent_map_0[] = { > + { P_BI_TCXO, 0 }, > + { P_AV1E_CC_PLL0_OUT_MAIN, 1 }, > + { P_AV1E_CC_PLL0_OUT_ODD, 2 }, > + { P_AV1E_CC_PLL0_OUT_EVEN, 3 }, > +}; > + > +static const struct clk_parent_data av1e_cc_parent_data_0[] = { > + { .index = DT_BI_TCXO }, > + { .hw = &av1e_cc_pll0.clkr.hw }, > + { .hw = &av1e_cc_pll0.clkr.hw }, > + { .hw = &av1e_cc_pll0.clkr.hw }, > +}; > + > +static const struct parent_map av1e_cc_parent_map_1[] = { > + { P_BI_TCXO, 0 }, > +}; > + > +static const struct clk_parent_data av1e_cc_parent_data_1[] = { > + { .index = DT_BI_TCXO }, > +}; > + > +static const struct freq_tbl ftbl_av1e_cc_av1e_core_clk_src[] = { > + F(300000000, P_AV1E_CC_PLL0_OUT_MAIN, 2, 0, 0), > + F(400000000, P_AV1E_CC_PLL0_OUT_MAIN, 2, 0, 0), > + F(600000000, P_AV1E_CC_PLL0_OUT_MAIN, 2, 0, 0), > + { } > +}; > + > +static struct clk_rcg2 av1e_cc_av1e_core_clk_src = { > + .cmd_rcgr = 0x4018, > + .mnd_width = 0, > + .hid_width = 5, > + .parent_map = av1e_cc_parent_map_0, > + .freq_tbl = ftbl_av1e_cc_av1e_core_clk_src, > + .hw_clk_ctrl = true, > + .clkr.hw.init = &(const struct clk_init_data) { > + .name = "av1e_cc_av1e_core_clk_src", > + .parent_data = av1e_cc_parent_data_0, > + .num_parents = ARRAY_SIZE(av1e_cc_parent_data_0), > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_rcg2_shared_ops, > + }, > +}; > + > +static const struct freq_tbl ftbl_av1e_cc_av1e_xo_clk_src[] = { > + F(19200000, P_BI_TCXO, 1, 0, 0), > + { } > +}; > + > +static struct clk_rcg2 av1e_cc_av1e_xo_clk_src = { > + .cmd_rcgr = 0x601c, > + .mnd_width = 0, > + .hid_width = 5, > + .parent_map = av1e_cc_parent_map_1, > + .freq_tbl = ftbl_av1e_cc_av1e_xo_clk_src, > + .hw_clk_ctrl = true, > + .clkr.hw.init = &(const struct clk_init_data) { > + .name = "av1e_cc_av1e_xo_clk_src", > + .parent_data = av1e_cc_parent_data_1, > + .num_parents = ARRAY_SIZE(av1e_cc_parent_data_1), > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_rcg2_shared_ops, Can it be just rcg2_ops? > + }, > +}; > + > +static struct clk_regmap_div av1e_cc_av1e_noc_ahb_div_clk_src = { > + .reg = 0x5020, > + .shift = 0, > + .width = 4, > + .clkr.hw.init = &(const struct clk_init_data) { > + .name = "av1e_cc_av1e_noc_ahb_div_clk_src", > + .parent_hws = (const struct clk_hw*[]) { > + &av1e_cc_av1e_core_clk_src.clkr.hw, > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_regmap_div_ro_ops, > + }, > +}; > + > +static struct clk_branch av1e_cc_ahb_clk = { > + .halt_reg = 0x6000, > + .halt_check = BRANCH_HALT_VOTED, > + .clkr = { > + .enable_reg = 0x6000, > + .enable_mask = BIT(0), > + .hw.init = &(const struct clk_init_data) { > + .name = "av1e_cc_ahb_clk", > + .parent_hws = (const struct clk_hw*[]) { > + &av1e_cc_av1e_noc_ahb_div_clk_src.clkr.hw, > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_branch2_ops, > + }, > + }, > +}; > + > +static struct clk_branch av1e_cc_av1e_core_apb_clk = { > + .halt_reg = 0x4044, > + .halt_check = BRANCH_HALT, > + .clkr = { > + .enable_reg = 0x4044, > + .enable_mask = BIT(0), > + .hw.init = &(const struct clk_init_data) { > + .name = "av1e_cc_av1e_core_apb_clk", > + .parent_hws = (const struct clk_hw*[]) { > + &av1e_cc_av1e_core_clk_src.clkr.hw, > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_branch2_ops, > + }, > + }, > +}; > + > +static struct clk_branch av1e_cc_av1e_core_axi_clk = { > + .halt_reg = 0x4040, > + .halt_check = BRANCH_HALT, > + .clkr = { > + .enable_reg = 0x4040, > + .enable_mask = BIT(0), > + .hw.init = &(const struct clk_init_data) { > + .name = "av1e_cc_av1e_core_axi_clk", > + .parent_hws = (const struct clk_hw*[]) { > + &av1e_cc_av1e_core_clk_src.clkr.hw, > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_branch2_ops, > + }, > + }, > +}; > + > +static struct clk_branch av1e_cc_av1e_core_clk = { > + .halt_reg = 0x4030, > + .halt_check = BRANCH_HALT, > + .clkr = { > + .enable_reg = 0x4030, > + .enable_mask = BIT(0), > + .hw.init = &(const struct clk_init_data) { > + .name = "av1e_cc_av1e_core_clk", > + .parent_hws = (const struct clk_hw*[]) { > + &av1e_cc_av1e_core_clk_src.clkr.hw, > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_branch2_ops, > + }, > + }, > +}; > + > +static struct clk_branch av1e_cc_av1e_gdsc_noc_ahb_clk = { > + .halt_reg = 0x5024, > + .halt_check = BRANCH_HALT, > + .clkr = { > + .enable_reg = 0x5024, > + .enable_mask = BIT(0), > + .hw.init = &(const struct clk_init_data) { > + .name = "av1e_cc_av1e_gdsc_noc_ahb_clk", > + .parent_hws = (const struct clk_hw*[]) { > + &av1e_cc_av1e_noc_ahb_div_clk_src.clkr.hw, > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_branch2_ops, > + }, > + }, > +}; > + > +static struct clk_branch av1e_cc_av1e_noc_ahb_clk = { > + .halt_reg = 0x5028, > + .halt_check = BRANCH_HALT_VOTED, > + .clkr = { > + .enable_reg = 0x5028, > + .enable_mask = BIT(0), > + .hw.init = &(const struct clk_init_data) { > + .name = "av1e_cc_av1e_noc_ahb_clk", > + .parent_hws = (const struct clk_hw*[]) { > + &av1e_cc_av1e_noc_ahb_div_clk_src.clkr.hw, > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_branch2_ops, > + }, > + }, > +}; > + > +static struct clk_branch av1e_cc_av1e_noc_core_axi_clk = { > + .halt_reg = 0x5004, > + .halt_check = BRANCH_HALT, > + .clkr = { > + .enable_reg = 0x5004, > + .enable_mask = BIT(0), > + .hw.init = &(const struct clk_init_data) { > + .name = "av1e_cc_av1e_noc_core_axi_clk", > + .parent_hws = (const struct clk_hw*[]) { > + &av1e_cc_av1e_core_clk_src.clkr.hw, > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_branch2_ops, > + }, > + }, > +}; > + > +static struct clk_branch av1e_cc_av1e_noc_xo_clk = { > + .halt_reg = 0x6038, > + .halt_check = BRANCH_HALT, > + .clkr = { > + .enable_reg = 0x6038, > + .enable_mask = BIT(0), > + .hw.init = &(const struct clk_init_data) { > + .name = "av1e_cc_av1e_noc_xo_clk", > + .parent_hws = (const struct clk_hw*[]) { > + &av1e_cc_av1e_xo_clk_src.clkr.hw, > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_branch2_ops, > + }, > + }, > +}; > + > +static struct gdsc av1e_cc_core_gdsc = { > + .gdscr = 0x4004, > + .en_rest_wait_val = 0x2, > + .en_few_wait_val = 0x2, > + .clk_dis_wait_val = 0xf, > + .pd = { > + .name = "av1e_cc_core_gdsc", > + }, > + .pwrsts = PWRSTS_OFF_ON, > + .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, Will AV1 consumer have any HW_CTRL requirement? > +}; > + > +static struct clk_regmap *av1e_cc_glymur_clocks[] = { > + [AV1E_CC_AHB_CLK] = &av1e_cc_ahb_clk.clkr, > + [AV1E_CC_AV1E_CORE_APB_CLK] = &av1e_cc_av1e_core_apb_clk.clkr, > + [AV1E_CC_AV1E_CORE_AXI_CLK] = &av1e_cc_av1e_core_axi_clk.clkr, > + [AV1E_CC_AV1E_CORE_CLK] = &av1e_cc_av1e_core_clk.clkr, > + [AV1E_CC_AV1E_CORE_CLK_SRC] = &av1e_cc_av1e_core_clk_src.clkr, > + [AV1E_CC_AV1E_GDSC_NOC_AHB_CLK] = &av1e_cc_av1e_gdsc_noc_ahb_clk.clkr, > + [AV1E_CC_AV1E_NOC_AHB_CLK] = &av1e_cc_av1e_noc_ahb_clk.clkr, > + [AV1E_CC_AV1E_NOC_AHB_DIV_CLK_SRC] = &av1e_cc_av1e_noc_ahb_div_clk_src.clkr, > + [AV1E_CC_AV1E_NOC_CORE_AXI_CLK] = &av1e_cc_av1e_noc_core_axi_clk.clkr, > + [AV1E_CC_AV1E_NOC_XO_CLK] = &av1e_cc_av1e_noc_xo_clk.clkr, > + [AV1E_CC_AV1E_XO_CLK_SRC] = &av1e_cc_av1e_xo_clk_src.clkr, > + [AV1E_CC_PLL0] = &av1e_cc_pll0.clkr, > +}; > + > +static struct gdsc *av1e_cc_glymur_gdscs[] = { > + [AV1E_CC_CORE_GDSC] = &av1e_cc_core_gdsc, > +}; > + > +static const struct qcom_reset_map av1e_cc_glymur_resets[] = { > + [AV1E_CC_AV1E_CORE_AXI_CLK_ARES] = { 0x4040, 2 }, > + [AV1E_CC_AV1E_CORE_CLK_ARES] = { 0x4030, 2 }, > + [AV1E_CC_AV1E_GDSC_NOC_AHB_CLK_ARES] = { 0x5024, 2 }, > + [AV1E_CC_AV1E_NOC_CORE_AXI_CLK_ARES] = { 0x5004, 2 }, > + [AV1E_CC_AV1E_NOC_XO_CLK_ARES] = { 0x6038, 2 }, > + [AV1E_CC_CORE_BCR] = { 0x4000 }, > + [AV1E_CC_NOC_BCR] = { 0x5000 }, > +}; > + > +static struct clk_alpha_pll *av1e_cc_glymur_plls[] = { > + &av1e_cc_pll0, > +}; > + > +static const u32 av1e_cc_glymur_critical_cbcrs[] = { > + 0x6034, /* AV1E_CC_AV1E_CC_XO_CLK */ > + 0x6054, /* AV1E_CC_SLEEP_CLK */ > +}; > + > +static const struct regmap_config av1e_cc_glymur_regmap_config = { > + .reg_bits = 32, > + .reg_stride = 4, > + .val_bits = 32, > + .max_register = 0xa01c, > + .fast_io = true, > +}; > + > +static const struct qcom_cc_driver_data av1e_cc_glymur_driver_data = { > + .alpha_plls = av1e_cc_glymur_plls, > + .num_alpha_plls = ARRAY_SIZE(av1e_cc_glymur_plls), > + .clk_cbcrs = av1e_cc_glymur_critical_cbcrs, > + .num_clk_cbcrs = ARRAY_SIZE(av1e_cc_glymur_critical_cbcrs), > +}; > + > +static const struct qcom_cc_desc av1e_cc_glymur_desc = { > + .config = &av1e_cc_glymur_regmap_config, > + .clks = av1e_cc_glymur_clocks, > + .num_clks = ARRAY_SIZE(av1e_cc_glymur_clocks), > + .resets = av1e_cc_glymur_resets, > + .num_resets = ARRAY_SIZE(av1e_cc_glymur_resets), > + .gdscs = av1e_cc_glymur_gdscs, > + .num_gdscs = ARRAY_SIZE(av1e_cc_glymur_gdscs), > + .use_rpm = true, > + .driver_data = &av1e_cc_glymur_driver_data, > +}; > + > +static const struct of_device_id av1e_cc_glymur_match_table[] = { > + { .compatible = "qcom,glymur-av1ecc" }, > + { } > +}; > +MODULE_DEVICE_TABLE(of, av1e_cc_glymur_match_table); > + > +static int av1e_cc_glymur_probe(struct platform_device *pdev) > +{ > + return qcom_cc_probe(pdev, &av1e_cc_glymur_desc); > +} > + > +static struct platform_driver av1e_cc_glymur_driver = { > + .probe = av1e_cc_glymur_probe, > + .driver = { > + .name = "av1ecc-glymur", > + .of_match_table = av1e_cc_glymur_match_table, > + }, > +}; > + > +module_platform_driver(av1e_cc_glymur_driver); > + > +MODULE_DESCRIPTION("QTI AV1ECC Glymur Driver"); > +MODULE_LICENSE("GPL"); > -- Thanks, Taniya Das