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[103.229.16.4]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-3b07c583d0asm3915104a91.3.2026.11.03.02.50.03 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 03 Nov 2026 02:50:08 -0800 (PST) Message-ID: Date: Tue, 3 Nov 2026 18:50:02 +0800 X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 2/4] phy: qcom: qmp-pcie: Add qref and refgen regulator vote for QCS8300 and SA8775p PHY To: Konrad Dybcio , Vinod Koul , Neil Armstrong , Manivannan Sadhasivam , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio , Abel Vesa Cc: Dmitry Baryshkov , peter.chen@oss.qualcomm.com, qiang.yu@oss.qualcomm.com, linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20260916102023.2054761-1-ziyue.zhang@oss.qualcomm.com> <20260916102023.2054761-3-ziyue.zhang@oss.qualcomm.com> Content-Language: en-US From: Ziyue Zhang In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Proofpoint-GUID: aOriWf7WT45-uy-hAFsUMO21_LfZd5G1 X-Proofpoint-Spam-Info: AW1haW4tMjYxMTAzMDA0MyBTYWx0ZWRfXyVyPHAr1VsDp CBQm/WiOElCUH9Z3qNZog9U6VMHEzmj1/mGUGHHRtceyC8f8TC9z05tTGT/bibbgQ4XSw8lLkmh kyJ/7FgMRTIvH3UzSWXNm2bv59ntyck= X-Authority-Analysis: v=2.4 cv=RZ0FmFtv c=1 sm=1 tr=0 ts=6ae9bc62 cx=c_pps a=UNFcQwm+pnOIJct1K4W+Mw==:117 a=nuhDOHQX5FNHPW3J6Bj6AA==:17 a=IkcTkHD0fZMA:10 a=zJRp6_cAMcgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yx91gb_oNiZeI1HMLzn7:22 a=EUspDBNiAAAA:8 a=3v8O9tVSiMwV8kAMF3cA:9 a=QEXdDO2ut3YA:10 a=uKXjsCUrEbL0IQVhDsJ9:22 X-Proofpoint-ORIG-GUID: aOriWf7WT45-uy-hAFsUMO21_LfZd5G1 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYxMTAzMDA0MyBTYWx0ZWRfXyxBznGtebCHL QFXmM1pv9vTlJyiaTC9/2hZxDewSS/d5JlmV8ppjskuJ34Uife86kW9161loWdR0dAsClLFU70f eVx0pJ0+dT9iDLJgN+1WU67E8WY7SDlk2FgxzMTCyvXkkDaCaXmRQnL7KWHbpcMfZmJCymU0k8o I0QZQQ4DcKudhBrEjITvZ9uIcvtq7K4HJ1GOaHdm8bLM/KBdSo5T64eoNw/cubMDxBEnS4Pj9FY d6CRV+jALxOuijyIr29Jsb4bUp0KcuOZds6Svb8No5q13UHBfCslUMPUEX++7NQTzu2S6FzNPVc NgQMUJqEVoYFEHaR4d0SWtLPdgBZjJarc3ZFHLqvseuJOfTwtUQw8eunpcFtj61PZqY8VTIfKgi UyJbXch9K4QIQxBxsthHvmAfTXh2H1kM7Wy2ogx6TOL6raDpo6+gHtOSJcbQunO06ar0iV6Z5/N e4BrTB6h0qKEDdApszw== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.138,FMLib:17.12.100.49 definitions=2026-11-03_02,2026-11-02_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 bulkscore=0 impostorscore=0 phishscore=0 suspectscore=0 adultscore=0 lowpriorityscore=0 spamscore=0 malwarescore=0 clxscore=1015 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2610300000 definitions=main-2611030043 On 10/28/2026 10:37 PM, Konrad Dybcio wrote: > On 9/16/26 12:20 PM, Ziyue Zhang wrote: >> Add a new sa8775p_qmp_phy_vreg_l that includes vdda-phy, vdda-pll, >> vdda-qref, vdda-refgen and refgen supplies, and use it for QCS8300 >> and SA8775p PCIe PHY configurations. This avoids modifying >> sm8550_qmp_phy_vreg_l and breaking SM8550 and SM8650. >> >> These supplies were missing from the original driver, which was found >> to be the root cause of occasional system crashes observed on QCS8300 >> and SA8775p platforms. Without voting for these supplies, the PCIe PHY >> lacks stable reference clock and voltage, so the PHY never becomes >> ready and initialization times out: >> >> [ 7.303119] qcom-qmp-pcie-phy 1c04000.phy: phy initialization timed-out >> [ 7.309948] phy phy-1c04000.phy.0: phy poweron failed --> -110 >> >> Note that due to a hardware issue, QREF actually depends on refgen3 >> rather than refgen2 as documented; refgen3 is therefore voted manually >> via the refgen supply as a workaround. >> >> Fixes: a05b6d5135ec ("phy: qcom-qmp-pcie: add support for sa8775p") >> Fixes: ebf198f17b5a ("phy: qcom-qmp-pcie: add dual lane PHY support for QCS8300") >> Signed-off-by: Ziyue Zhang >> --- >> drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 16 ++++++++++------ >> 1 file changed, 10 insertions(+), 6 deletions(-) >> >> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c >> index da83358c97ea..ab81c6e584a8 100644 >> --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c >> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c >> @@ -4094,6 +4094,10 @@ static const char * const sm8550_qmp_phy_vreg_l[] = { >> "vdda-phy", "vdda-pll", "vdda-qref", >> }; >> >> +static const char * const sa8775p_qmp_phy_vreg_l[] = { >> + "vdda-phy", "vdda-pll", "vdda-qref", "vdda-refgen", "refgen", >> +}; > I think we could grab them unconditionally, as QREF/REFGEN appears > on most/all SoCs (perhaps with regulator_optional_get so that we > defer the correctness of this to dt-bindings for any specific > platform) > > Konrad Hi Konrad I think that on future platforms, qref will be voted by the tcsr driver or another driver, depending on where those registers are located. The PHY driver will only need to vote for refgen1p2 and refgen0p9. If future platforms need to vote for vdda-qref, vdda-refgen, and refgen, they can simply reuse this vreg_list. BR Ziyue