From: Mark Brown <broonie@kernel.org>
To: Andy Shevchenko <andy.shevchenko@gmail.com>
Cc: Linus Walleij <linus.walleij@linaro.org>,
Patrick Rudolph <patrick.rudolph@9elements.com>,
naresh.solanki@9elements.com, linux-gpio@vger.kernel.org,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH] pinctrl: cy8c95x0: Cache muxed registers
Date: Tue, 14 May 2024 10:02:17 +0100 [thread overview]
Message-ID: <d4c03f3b-a8ce-44bd-8897-8a2f276dede6@sirena.org.uk> (raw)
In-Reply-To: <CAHp75VfA8G6KyhD5_HDyKWp5AdpsnnQ27gzTDRRjDRCVXkT-ag@mail.gmail.com>
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On Tue, May 14, 2024 at 11:55:06AM +0300, Andy Shevchenko wrote:
> It's about introducing pages of virtual registers (from regmap p.o.v.)
> to access the banks of selectable registers. The cache most likely
> will be the same, i.e. MAPPLE_TREE.
If there's paging of registers then regmap supports this with the ranges
feature, you can tell regmap where the window is in the physical
register map and which register to use to switch pages and have regmap
export the underlying registers as a linear range of virtual registers.
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next prev parent reply other threads:[~2024-05-14 9:02 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-12-19 12:53 Patrick Rudolph
2023-12-20 12:04 ` Linus Walleij
2024-05-14 5:27 ` Andy Shevchenko
2024-05-14 7:49 ` Linus Walleij
2024-05-14 8:39 ` Patrick Rudolph
2024-05-14 8:51 ` Linus Walleij
2024-05-14 8:55 ` Andy Shevchenko
2024-05-14 8:57 ` Andy Shevchenko
2024-05-14 9:02 ` Mark Brown [this message]
2024-05-14 9:23 ` Andy Shevchenko
2024-05-14 9:30 ` Mark Brown
2024-05-14 8:55 ` Mark Brown
2024-05-16 17:03 ` Patrick Rudolph
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