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Mon, 02 Nov 2026 07:56:04 -0800 (PST) Received: from [192.168.226.81] ([178.235.128.140]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-c4cebefcdfasm3479566b.36.2026.11.02.07.56.02 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 02 Nov 2026 07:56:03 -0800 (PST) Message-ID: Date: Mon, 2 Nov 2026 16:56:01 +0100 X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3] mailbox: qcom-cpucp: read mbox hardware register using readq() To: Sivansh Gupta Cc: Sibi Sankar , Jassi Brar , Konrad Dybcio , linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org References: <20260928052940.688105-1-sivansh.gupta@oss.qualcomm.com> <989045f1-c4c3-4871-92b5-dc9f2a18f801@oss.qualcomm.com> <179189473286.2132802.7434637844183959510.b4-reply@b4> Content-Language: en-US From: Konrad Dybcio In-Reply-To: <179189473286.2132802.7434637844183959510.b4-reply@b4> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Authority-Analysis: v=2.4 cv=KZ1HIgYD c=1 sm=1 tr=0 ts=6ae8b296 cx=c_pps a=1Os3MKEOqt8YzSjcPV0cFA==:117 a=PRfkaYvzSr8QmIIGAkY2Sg==:17 a=IkcTkHD0fZMA:10 a=zJRp6_cAMcgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=gowsoOTTUOVcmtlkKump:22 a=VwQbUJbxAAAA:8 a=EUspDBNiAAAA:8 a=ydoro5LrJAMts5ZGCqMA:9 a=QEXdDO2ut3YA:10 a=hhpmQAJR8DioWGSBphRh:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYxMTAyMDA2MyBTYWx0ZWRfX6not845izkyN wPxsYH4OZQGNiTAqO6vHEu1JnihZrvYXOk/LAJnz2CGtYeoWUBtlFW9jtIriRPyCY2VMagdLl4l nxn+s2ZJJtyqo6nXRKSXoc9O7gZ8VKIMxfS5TWMv2uFWRjTHQQAnCSZPl7sHWZP1fkvLZWdoV9Z G9KEzNDLNYkUatjAxUNdDzYsesmHnN2FktAwQ/p7L4941Fnnog9rU9C37ppl7PCFAbFLKdaUoF4 gLIl/s4Jz1Awy5JZeiib905ZUrMjUN2u0Q4K6xj5DU04LAqrx7mnxvtChEDHsvx/8mOFS6P1A8C hFMaG7jijJef4LLwywkwCII2bwsyZSCCGpDvN5lNChFVl956R+w9gwV0y5WaVoVyMp37GT+7n95 DWHNjxQHEJdJ6+o/UegTFoDMcEPDjTRQw1FExVHfWwm2gsepRjuIjTBrEl1Fx0/oFD2knvRWpLX ZfW+Qr+GxFscHq4CL3Q== X-Proofpoint-Spam-Info: AW1haW4tMjYxMTAyMDA2MyBTYWx0ZWRfX6jIZQ9Ga1e4g T17SwpNrHieVZhPyAfbjmosIg7kc5MjZSRnXIHY6d5zTK9H1gO1mmEbk1O1qVUKW6qH95oWND2a F99Nwk0GJQizYo/RCLEXHXZ0PeMOfps= X-Proofpoint-ORIG-GUID: ECXm3uXvZePW6u_6d_yOIqvbJjritKlH X-Proofpoint-GUID: ECXm3uXvZePW6u_6d_yOIqvbJjritKlH X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.138,FMLib:17.12.100.49 definitions=2026-11-02_04,2026-11-02_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 clxscore=1015 suspectscore=0 bulkscore=0 priorityscore=1501 malwarescore=0 impostorscore=0 phishscore=0 adultscore=0 spamscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2610300000 definitions=main-2611020063 On 10/13/26 2:32 PM, Sivansh Gupta wrote: > On 2026-09-30 11:55 +0200, Konrad Dybcio wrote: >> On 9/28/26 7:29 AM, Sivansh Gupta wrote: >>> Mailbox hardware registers are 64 bit wide, but the interrupt handler >>> currently reads only 32 bits with readl() at offset 0x4 (upper 32 >>> bits). This returns an incorrect value, while reading using readq() >>> returns the expected value. >>> >>> Use readq() to access the 64 bit register and pass the expected value >>> to the mailbox client. >>> >>> Fixes: 0e2a9a03106c ("mailbox: Add support for QTI CPUCP mailbox controller") >>> Signed-off-by: Sivansh Gupta >>> --- >>> v3: >>> - Removed references to an out of tree driver to focus on the incorrect >>> value returned by readl() >>> https://lore.kernel.org/all/93ce8588-7500-45da-9b9a-424c202590cf@oss.qualcomm.com/#t >>> >>> v2: >>> - Expanded the commit message to explain why this change is required. >>> >>> drivers/mailbox/qcom-cpucp-mbox.c | 2 +- >>> 1 file changed, 1 insertion(+), 1 deletion(-) >>> >>> diff --git a/drivers/mailbox/qcom-cpucp-mbox.c b/drivers/mailbox/qcom-cpucp-mbox.c >>> index 862e45e8fbd5..0b584d9aad6c 100644 >>> --- a/drivers/mailbox/qcom-cpucp-mbox.c >>> +++ b/drivers/mailbox/qcom-cpucp-mbox.c >>> @@ -61,7 +61,7 @@ static irqreturn_t qcom_cpucp_mbox_irq_fn(int irq, void *data) >>> status = readq(cpucp->rx_base + APSS_CPUCP_RX_MBOX_STAT); >>> >>> for_each_set_bit(i, (unsigned long *)&status, cpucp->mbox.num_chans) { >>> - u32 val = readl(cpucp->rx_base + APSS_CPUCP_RX_MBOX_CMD(i) + APSS_CPUCP_MBOX_CMD_OFF); >> >> This still retains the writel() later on > > This is intentional, currently the existing mbox client(s) assume 32 bits > writes instead of 64 bits, changing to 64 bits here would require all > mbox clients to be updated to send 64 bits. > Currently there is only 1 upstream client (arm_scmi). > >>> + u64 val = readq(cpucp->rx_base + APSS_CPUCP_RX_MBOX_CMD(i)); >> >> This will alter the indices of the mailbox channels, but it's ""fine"" >> because it's always zero for the existing platforms.. >> >> Konrad > > I am unsure what you mean here. The channel registers are spaced 8 bytes > apart. In the old code, we used to read each channel's upper 32 bits > (channel base + 4 bytes), in the new code we will be reading the entire > 8 bytes. > If this is not what you meant, please let me know! You're right, please remove the leftover define Reviewed-by: Konrad Dybcio Konrad