Re: [PATCH net-next v5 1/3] net: macb: add QUEUE_DISABLE capability to 3 compatibles

[Nicolai Buchwitz <nb@tipi-net.de>]

Hi Théo

On 16.10.2026 18:58, Théo Lebrun wrote:
> From datasheets, we know those 3 IP versions support Tx and Rx queue
> disabling, ie bit 0 in RBQP and TBQP registers.

nit: Just learned that git am will turn this into >From. Maybe reword 
the first sentence.

> 
> All revisions I've seen either support it on both Tx & Rx or don't
> support it at all.
> 
> Sources:
> 
>    Compatible            | Match data         | Datasheet
>    
> ----------------------|--------------------|-------------------------
>    atmel,sama5d29-gem    | sama5d29_config    | DS60001764 [0]
>    microchip,mpfs-macb   | mpfs_config        | header files [1]
>    microchip,sama7g5-gem | sama7g5_gem_config | DS60001765 [2]
> 
> To contrast, check out the SAM9X60 DS60001579C datasheet [3] that does
> not document bit 0 as anything special on page 1041 and page 1042.
> 
> [0]:
> https://ww1.microchip.com/downloads/aemDocuments/documents/MPU32/ProductDocuments/DataSheets/SAMA5D29-Data-Sheet-ds60001764.pdf
> 
> [1]:
> https://github.com/polarfire-soc/polarfire-soc-bare-metal-library/blob/614a67ab/src/platform/drivers/mss/mss_ethernet_mac/mss_ethernet_mac_regs.h#L200-L207
> 
> [2]:
> https://ww1.microchip.com/downloads/aemDocuments/documents/MPU32/ProductDocuments/DataSheets/SAMA7G5-Series-Data-Sheet-DS60001765.pdf
> 
> [3]:
> https://ww1.microchip.com/downloads/en/DeviceDoc/SAM9X60-Data-Sheet-DS60001579C.pdf
> 
> Signed-off-by: Théo Lebrun <theo.lebrun@bootlin.com>
> ---
>  drivers/net/ethernet/cadence/macb_main.c | 7 ++++---
>  1 file changed, 4 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/net/ethernet/cadence/macb_main.c 
> b/drivers/net/ethernet/cadence/macb_main.c
> index 020a47353d01..625171fd3f9b 100644
> --- a/drivers/net/ethernet/cadence/macb_main.c
> +++ b/drivers/net/ethernet/cadence/macb_main.c
> @@ -5743,7 +5743,7 @@ static const struct macb_config sama5d2_config = 
> {
> 
>  static const struct macb_config sama5d29_config = {
>  	.caps = MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII | MACB_CAPS_GEM_HAS_PTP |
> -		MACB_CAPS_USRIO_HAS_MII,
> +		MACB_CAPS_USRIO_HAS_MII | MACB_CAPS_QUEUE_DISABLE,

AFAIU this also switches WoL suspend on these SoCs from the tieoff ring 
to
QUEUE_DISABLE. Was WoL tested on any of them? Worth a line in the commit
message too.

>  	.dma_burst_length = 16,
>  	.usrio = &at91_default_usrio,
>  };
> @@ -5799,7 +5799,8 @@ static const struct macb_config mpfs_config = {
>  	.caps = MACB_CAPS_GIGABIT_MODE_AVAILABLE |
>  		MACB_CAPS_JUMBO |
>  		MACB_CAPS_GEM_HAS_PTP |
> -		MACB_CAPS_USRIO_HAS_TSUCLK_SOURCE,
> +		MACB_CAPS_USRIO_HAS_TSUCLK_SOURCE |
> +		MACB_CAPS_QUEUE_DISABLE,
>  	.dma_burst_length = 16,
>  	.init = init_reset_optional,
>  	.usrio = &mpfs_usrio,
> @@ -5812,7 +5813,7 @@ static const struct macb_config 
> sama7g5_gem_config = {
>  		MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII |
>  		MACB_CAPS_USRIO_HAS_REFCLK_SOURCE |
>  		MACB_CAPS_MIIONRGMII | MACB_CAPS_GEM_HAS_PTP |
> -		MACB_CAPS_USRIO_HAS_MII,
> +		MACB_CAPS_USRIO_HAS_MII | MACB_CAPS_QUEUE_DISABLE,
>  	.dma_burst_length = 16,
>  	.usrio = &sama7g5_gem_usrio,
>  };

Thanks,
Nicolai