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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b8dbefc69ebsm244806166b.20.2026.01.29.02.32.55 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 29 Jan 2026 02:32:56 -0800 (PST) Message-ID: Date: Thu, 29 Jan 2026 11:32:54 +0100 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 1/3] dt-bindings: interconnect: qcom,qcs8300-rpmh: add clocks property to enable QoS To: Odelu Kukatla , Georgi Djakov , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio Cc: Raviteja Laggyshetty , Dmitry Baryshkov , Bartosz Golaszewski , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Mike Tipton References: <20260127090116.1438780-1-odelu.kukatla@oss.qualcomm.com> <20260127090116.1438780-2-odelu.kukatla@oss.qualcomm.com> <5b62fc63-314e-40a0-a975-9df75ec49e9a@oss.qualcomm.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMTI5MDA2OSBTYWx0ZWRfX7rXFKDUGSSSy o4mVgw151V+Z8My4YW0QvslnipaV2+hvYqdKLRqNHPPLshzJaQl6GZuZ5fNA8AGFo+bNws1ybOC QudB1VrPS8bbk1+n2NMrMgGaz0JtcTBW/rjWHnze4WMM0pAQGxjuA9QpdNBC7cbSMklIv2P3doB FrfG/ZbTHUt21JuYmfixXHDC8cxeK8FbqxurStn2H5/tSAAFaNhv1jbjOFG0p7Snrhi0ZWjmLhY cGxL6mP/E0drtEbe5UKI9wipx+AE7bbfWSO5s5XPHue/4ujrJnPapQo24OkMaCK+VP4eF7IO8BB DeAOaX3aLbMfrHeAiWGWRdSOV3fzeYjsraIMXcxeiV/utC49/gqa3/lMMs12CPWaWFJlIOvZirf MVA4UxhuaaXKJOjHu11lvpKuD4nRB4HZ17RiBCybCHTlveZLMd/vUJVjuFjORWdmC65tYDEeatH 6iTSd1uwm+JC9cc33JQ== X-Authority-Analysis: v=2.4 cv=QpRTHFyd c=1 sm=1 tr=0 ts=697b375a cx=c_pps a=oc9J++0uMp73DTRD5QyR2A==:117 a=FpWmc02/iXfjRdCD7H54yg==:17 a=IkcTkHD0fZMA:10 a=vUbySO9Y5rIA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=WMlQ1W5rKAuT8PP_VscA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=iYH6xdkBrDN1Jqds4HTS:22 X-Proofpoint-GUID: UWtI3x_4z-JUvU1B2QCYIDHdiR3_c2nj X-Proofpoint-ORIG-GUID: UWtI3x_4z-JUvU1B2QCYIDHdiR3_c2nj X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-01-29_02,2026-01-28_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 lowpriorityscore=0 clxscore=1015 priorityscore=1501 phishscore=0 impostorscore=0 bulkscore=0 malwarescore=0 spamscore=0 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2601150000 definitions=main-2601290069 On 1/29/26 11:10 AM, Odelu Kukatla wrote: > > > On 1/27/2026 4:24 PM, Konrad Dybcio wrote: >> On 1/27/26 10:01 AM, Odelu Kukatla wrote: >>> Some QCS8300 interconnect nodes have QoS registers located inside >>> a block whose interface is clock-gated. For those nodes, driver >>> must enable the corresponding clock(s) before accessing the >>> registers. Add the 'clocks' property so the driver can obtain >>> and enable the required clock(s). >>> >>> Only interconnects that have clock‑gated QoS register interface >>> use this property; it is not applicable to all interconnect nodes. >>> >>> Signed-off-by: Odelu Kukatla >>> --- [...] >>> + - if: >>> + properties: >>> + compatible: >>> + contains: >>> + enum: >>> + - qcom,qcs8300-aggre2-noc >>> + then: >>> + properties: >>> + clocks: >>> + items: >>> + - description: RPMH CC IPA clock >> >> LeMans also has ufscard clk here >> > > For aggre2 noc, QCS8300 does not integrate the ufscard controller > present on LeMans, so that clock is not part of the QCS8300 hardware. > The only QoS relevant clock on this node for QCS8300 is the RPMH CC IPA > clock, which is why only that one appears in the binding. Ohhh I forgot UFSCard translated to UFS1.. >>> + >>> + - if: >>> + properties: >>> + compatible: >>> + contains: >>> + enum: >>> + - qcom,qcs8300-gem-noc >>> + then: >>> + properties: >>> + clocks: >>> + items: >>> + - description: GCC DDRSS GPU AXI clock >> >> and lacks this one >> >> Are there actual reasons for these differences? >> > > The gem noc QoS interface on QCS8300 requires the DDRSS GPU AXI clock to > be enabled for QoS register access, so it is listed in the binding. The > difference is therefore due to SoC level differences. Alright, thanks Konrad