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Thu, 22 Oct 2026 04:00:28 -0700 (PDT) Received: from [192.168.226.26] ([178.235.128.140]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-c468a5ba26csm90719666b.62.2026.10.22.04.00.26 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 22 Oct 2026 04:00:28 -0700 (PDT) Message-ID: Date: Thu, 22 Oct 2026 13:00:19 +0200 X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v5 10/11] phy: qualcomm: qmp-combo: Fix Glymur v8 DP PHY init and configure sequences To: Nabige Aala , Vinod Koul , Neil Armstrong , Manivannan Sadhasivam , Dmitry Baryshkov , Wesley Cheng , Abel Vesa , Johan Hovold , Bjorn Andersson , Dmitry Baryshkov Cc: linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org, Ritesh Kumar , Mahadevan P References: <20261001-glymur-phy-v3-v5-0-3848c2615d5a@oss.qualcomm.com> <20261001-glymur-phy-v3-v5-10-3848c2615d5a@oss.qualcomm.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: <20261001-glymur-phy-v3-v5-10-3848c2615d5a@oss.qualcomm.com> Content-Type: text/plain; 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> + writel(0x87, qmp->dp_tx2 + QSERDES_V8_LALB_CLKBUF_ENABLE); The HPG asks to first write 0x8f to first [...] > + ret = readl_poll_timeout(qmp->dp_serdes + cfg->regs[QPHY_COM_CMN_STATUS], > + status, > + ((status & BIT(1)) > 0), > + 500, > + 10000); The programming guide doesn't ask to check this bit and the way I read the description of this bit within the register, bit0 already asserts this being true The rest is OK Konrad