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[88.112.131.206]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-5330d4202eesm1321910e87.234.2024.08.18.16.59.25 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sun, 18 Aug 2024 16:59:26 -0700 (PDT) Message-ID: Date: Mon, 19 Aug 2024 02:59:19 +0300 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 06/13] media: qcom: camss: csiphy-3ph: Use an offset variable to find common control regs To: Depeng Shao , rfoss@kernel.org, todor.too@gmail.com, bryan.odonoghue@linaro.org, mchehab@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org Cc: linux-arm-msm@vger.kernel.org, linux-media@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, kernel@quicinc.com References: <20240812144131.369378-1-quic_depengs@quicinc.com> <20240812144131.369378-7-quic_depengs@quicinc.com> Content-Language: en-US From: Vladimir Zapolskiy In-Reply-To: <20240812144131.369378-7-quic_depengs@quicinc.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 8/12/24 17:41, Depeng Shao wrote: > From: Bryan O'Donoghue > > New versions of the CSIPHY locate the control registers at offset 0x1000 > not offset 0x800. > > Provide a variable to base an offset from for the purposes of redirecting > the base offset for the new PHY regs layout. > > The existing setup bases from 0x800, the new from 0x1000 with some of the > 'EXT' registers dropped but the lower-order lane config regs at offset 0x00 > and up the same as before. > > Signed-off-by: Bryan O'Donoghue > Signed-off-by: Depeng Shao > --- > .../qcom/camss/camss-csiphy-3ph-1-0.c | 68 ++++++++++++------- > 1 file changed, 44 insertions(+), 24 deletions(-) > > diff --git a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c b/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c > index 93782ebfe0ea..1219a25ec55b 100644 > --- a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c > +++ b/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c > @@ -42,11 +42,11 @@ > #define CSIPHY_3PH_LNn_CSI_LANE_CTRL15(n) (0x03c + 0x100 * (n)) > #define CSIPHY_3PH_LNn_CSI_LANE_CTRL15_SWI_SOT_SYMBOL 0xb8 > > -#define CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(n) (0x800 + 0x4 * (n)) > +#define CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(offset, n) (offset + 0x4 * (n)) Macro value above shall be this one: ((offset) + 0x4 * (n)) > #define CSIPHY_3PH_CMN_CSI_COMMON_CTRL5_CLK_ENABLE BIT(7) > #define CSIPHY_3PH_CMN_CSI_COMMON_CTRL6_COMMON_PWRDN_B BIT(0) > #define CSIPHY_3PH_CMN_CSI_COMMON_CTRL6_SHOW_REV_ID BIT(1) > -#define CSIPHY_3PH_CMN_CSI_COMMON_STATUSn(n) (0x8b0 + 0x4 * (n)) > +#define CSIPHY_3PH_CMN_CSI_COMMON_STATUSn(offset, n) ((offset + 0xb0) + 0x4 * (n)) Macro value above shall be this one: ((offset) + 0xb0 + 0x4 * (n)) > #define CSIPHY_DEFAULT_PARAMS 0 > #define CSIPHY_LANE_ENABLE 1 > @@ -66,6 +66,7 @@ struct csiphy_lane_regs { > struct csiphy_device_regs { > const struct csiphy_lane_regs *lane_regs; > int lane_array_size; > + u32 offset; > }; > With two minor fixes above, Reviewed-by: Vladimir Zapolskiy -- Best wishes, Vladimir