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Thu, 29 Oct 2026 00:25:49 -0700 (PDT) Received: from [192.168.25.64] ([94.155.124.210]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-48e542ed998sm18038106f8f.13.2026.10.29.00.25.47 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 29 Oct 2026 00:25:49 -0700 (PDT) Message-ID: Date: Thu, 29 Oct 2026 09:25:46 +0200 X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 1/3] dt-bindings: clock: qcom,camcc-sm8250: add interconnect provider To: Bryan O'Donoghue , Atanas Filipov , Krzysztof Kozlowski , Dmitry Baryshkov Cc: Bjorn Andersson , Michael Turquette , Stephen Boyd , Konrad Dybcio , Georgi Djakov , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Abel Vesa , Jonathan Marek , Dmitry Baryshkov , Konrad Dybcio , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20261016170701.1504338-1-atanas.filipov@oss.qualcomm.com> <20261016170701.1504338-2-atanas.filipov@oss.qualcomm.com> <20261020-bloodhound-of-remarkable-debate-11afe3@quoll> <7ca815b3-4712-42e4-996d-4a1e53cad492@oss.qualcomm.com> <20261028181040.3515955-1-atanas.filipov@oss.qualcomm.com> Content-Language: en-US From: "Gjorgji Rosikopulos (Consultant)" In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-ORIG-GUID: o_P1Y0JUMQudwgmYHPVDQNBLA7EHuzF1 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYxMDI5MDAyOCBTYWx0ZWRfX/gSzRMCw2AMP r2iDbyDnInqA+6esZY+j/lmoTq8l3qYnb1R+En0OUgLjRia06RiAdGprkD7AzSS9pnNvnpbY8Ef xVTXlm3YbtCAFCrClLrNr4Pa6xoOGkAVlTVztqqX28Gz1UnVqjvhtZA2aNRSOsYDmsjRrFNO3V1 TCtBU2VYSWAKhW/Mzzuu9Zks6PiylnvHkjj4GUk+SQ9PHR6ch6YmeiY6X2S5VAT87+ir+sWxdie YISloJ9nVREyca0pMIDVZ2mtW/lHM3wAWkJ4ohbiCYmos8r47fq/DUuYbYrP1Xo1vZvHH/l/a8C mh8rOvdpu0QXemqlOZb6pPodgQtu+iRulNFwXuRu8tdkWkyulPfEGPbZQAZ4k/RCjvgOrNH9Q1h E82rO6VbSwYfWLbsIdke1TCsf9PrU0PdkhoQhOcbtfaiwX67N4ZUdWS31cwvO5uzCUnLb3m1C/5 kng9nshRYl2OxnqZ92Q== X-Proofpoint-GUID: o_P1Y0JUMQudwgmYHPVDQNBLA7EHuzF1 X-Proofpoint-Spam-Info: AW1haW4tMjYxMDI5MDAyOCBTYWx0ZWRfX3xn+GmMjAbR0 4hx58GIuE0CdrOxDsSiTxEgV5EQjPOsyK9GmArnLId8T2EUQfKLs3EbJy3qJqWjHBnf6FYF+snJ 1E1e8V0Mhf2FrsaSZ75JgkaI4fWuBKs= X-Authority-Analysis: v=2.4 cv=bYv+w+PB c=1 sm=1 tr=0 ts=6ae2f4ff cx=c_pps a=wEM5vcRIz55oU/E2lInRtA==:117 a=eGCDHFSXubCXFTSSGhjuOA==:17 a=IkcTkHD0fZMA:10 a=660iZSQnnn4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=eoimf2acIAo5FJnRuUoq:22 a=bB782UoiXxmDKwpK7Y8A:9 a=QEXdDO2ut3YA:10 a=OIgjcC2v60KrkQgK7BGD:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.138,FMLib:17.12.100.49 definitions=2026-10-29_02,2026-10-21_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 impostorscore=0 malwarescore=0 bulkscore=0 spamscore=0 phishscore=0 lowpriorityscore=0 clxscore=1015 adultscore=0 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2610190000 definitions=main-2610290028 On 10/29/2026 12:00 AM, Bryan O'Donoghue wrote: > On 28/10/2026 19:10, Atanas Filipov wrote: >> What clock votes cannot express is why I think the camera NoC is an >> interconnect: >> >> - The camera NoC is a bus with several independent masters: the VFE >> write ports, JPEG and OPE. They share it on the way to the MMSS NoC, >> and the camnoc AXI clock sets its throughput. > > I've always conceptually viewed the CamNoc as just another NoC that > happens to live inside of the TITAN_TOP_GDSC power-island. > > I think the trouble here is the CAMNOC_AXI_CLK is just one clock, it's > not interconnecting any two things at all. > > Noc entries in DT usually look like > > interconnects = <&gem_noc MASTER_AMPSS_M0 0 > &config_noc SLAVE_VENUS_CFG 0>, > <&mmss_noc MASTER_VIDEO_P0 0 &mc_virt SLAVE_EBI_CH0 0>; > interconnect-names = "cpu-cfg", "video-mem"; > > In the second case we're connecting an MMSS port to a DRAM port i.e. two > completely separate producers/consumers and we have specific ports that > RPM/RPMh is involved in managing. > > Which is not the case for CamNoc - here really we have some shared > clocks which we need to calculate across components within the Camera > power-island. > > In downstream the CPAs code does that. > > - icc-clk would I think over-provision clocks > - CCF would as you've observed under-provision > > - But a CPA's analog in upstream which components set/consume ? > > That would work. > > After all what we are doing here _is_ specific to how camera works. We > don't really have many - any ? other examples in Qcom SoCs where we lump > a number of different semi-independent components into one area - ICP, > CDM, VFE, JPEG and ask them to share aggregated clocks - in a way that > is specific to - guessing but - specific to how these components get > modeled in silicon test benches. > > My vote is to replicate CPAs in upstream with a CPA's icc provider driver. > > The bandwidth calculations are already proven out in downstream and if > we get it right - potentially its something downstream could switch to. > > We could even use the interconnect API inside of the CPA's driver but, I > think just doing votes via interconnect and icc_set_bw() into icc-clk in > the drivers directly won't produce the same bandwidth calculations we > have in downstream - which you may loathe downstream code but the clock > calculations we'd assume are ~ a pretty good starting point. > > So; make the CPAs driver an icc provider. > > cpas_icc_set() could/should absorb the downstream cam_cpas_hw.c > heuristic for calculating the aggregate clocks. > > Its not represented in generic icc-clk right now and as we add in more > clocks/SoCs this disparity will grow. Just to add, there is a CAMNOC interconnect within the camera subsystem that handles arbitration between the online and offline engines and routes the data to MMNOC. It also provides QoS settings, which are currently configured by the VFE driver as part of set_qos(). Therefore, I agree with Bryan that, if implemented properly, the downstream driver could switch to this approach in the future. This raises the question: should we update CAMSS to use the CAMNOC provider and stop voting directly on MMNOC? CAMNOC could then vote on MNOC based on the aggregated bandwidth requests from the individual engines. Regards, ~Gjorgji > > --- > bod