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Fri, 04 Apr 2025 07:45:39 -0700 (PDT) Received: from [192.168.0.20] ([212.21.159.224]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-5f08771a1c6sm2503812a12.11.2025.04.04.07.45.38 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 04 Apr 2025 07:45:39 -0700 (PDT) Message-ID: Date: Fri, 4 Apr 2025 17:45:37 +0300 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 3/6] x86/bugs: Fix RSB clearing in indirect_branch_prediction_barrier() To: Josh Poimboeuf , x86@kernel.org Cc: linux-kernel@vger.kernel.org, amit@kernel.org, kvm@vger.kernel.org, amit.shah@amd.com, thomas.lendacky@amd.com, bp@alien8.de, tglx@linutronix.de, peterz@infradead.org, pawan.kumar.gupta@linux.intel.com, corbet@lwn.net, mingo@redhat.com, dave.hansen@linux.intel.com, hpa@zytor.com, seanjc@google.com, pbonzini@redhat.com, daniel.sneddon@linux.intel.com, kai.huang@intel.com, sandipan.das@amd.com, boris.ostrovsky@oracle.com, Babu.Moger@amd.com, david.kaplan@amd.com, dwmw@amazon.co.uk, andrew.cooper3@citrix.com References: <27fe2029a2ef8bc0909e53e7e4c3f5b437242627.1743617897.git.jpoimboe@kernel.org> From: Nikolay Borisov Content-Language: en-US In-Reply-To: <27fe2029a2ef8bc0909e53e7e4c3f5b437242627.1743617897.git.jpoimboe@kernel.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit On 2.04.25 г. 21:19 ч., Josh Poimboeuf wrote: > IBPB is expected to clear the RSB. However, if X86_BUG_IBPB_NO_RET is > set, that doesn't happen. Make indirect_branch_prediction_barrier() > take that into account by calling __write_ibpb() which already does the > right thing. I find this changelog somewhat dubious. So zen < 4 basically have IBPB_NO_RET, your patch 2 in this series makes using SBPB for cores which have SRSO_NO or if the mitigation is disabled. So if you have a core which is zen <4 and doesn't use SBPB then what happens? > > Fixes: 50e4b3b94090 ("x86/entry: Have entry_ibpb() invalidate return predictions") > Signed-off-by: Josh Poimboeuf > --- > arch/x86/include/asm/nospec-branch.h | 6 +++--- > arch/x86/kernel/cpu/bugs.c | 1 - > 2 files changed, 3 insertions(+), 4 deletions(-) > > diff --git a/arch/x86/include/asm/nospec-branch.h b/arch/x86/include/asm/nospec-branch.h > index bbac79cad04c..f99b32f014ec 100644 > --- a/arch/x86/include/asm/nospec-branch.h > +++ b/arch/x86/include/asm/nospec-branch.h > @@ -514,11 +514,11 @@ void alternative_msr_write(unsigned int msr, u64 val, unsigned int feature) > : "memory"); > } > > -extern u64 x86_pred_cmd; > - > static inline void indirect_branch_prediction_barrier(void) > { > - alternative_msr_write(MSR_IA32_PRED_CMD, x86_pred_cmd, X86_FEATURE_IBPB); > + asm_inline volatile(ALTERNATIVE("", "call __write_ibpb", X86_FEATURE_IBPB) > + : ASM_CALL_CONSTRAINT > + :: "rax", "rcx", "rdx", "memory"); > } > > /* The Intel SPEC CTRL MSR base value cache */ > diff --git a/arch/x86/kernel/cpu/bugs.c b/arch/x86/kernel/cpu/bugs.c > index c8b8dc829046..9f9637cff7a3 100644 > --- a/arch/x86/kernel/cpu/bugs.c > +++ b/arch/x86/kernel/cpu/bugs.c > @@ -59,7 +59,6 @@ DEFINE_PER_CPU(u64, x86_spec_ctrl_current); > EXPORT_PER_CPU_SYMBOL_GPL(x86_spec_ctrl_current); > > u32 x86_pred_cmd __ro_after_init = PRED_CMD_IBPB; > -EXPORT_SYMBOL_GPL(x86_pred_cmd); > > static u64 __ro_after_init x86_arch_cap_msr; >