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Thu, 05 Sep 2024 04:54:43 +0000 (GMT) Received: from nalasex01b.na.qualcomm.com (nalasex01b.na.qualcomm.com [10.47.209.197]) by NALASPPMTA02.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 4854sgXF025037 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 5 Sep 2024 04:54:42 GMT Received: from [10.233.21.53] (10.80.80.8) by nalasex01b.na.qualcomm.com (10.47.209.197) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Wed, 4 Sep 2024 21:54:38 -0700 Message-ID: Date: Thu, 5 Sep 2024 12:54:35 +0800 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 17/19] arm64: defconfig: enable clock controller, interconnect and pinctrl for QCS8300 To: Krzysztof Kozlowski , Bjorn Andersson , Mathieu Poirier , Rob Herring , Conor Dooley , Bartosz Golaszewski , Konrad Dybcio CC: , , , , , References: <20240904-qcs8300_initial_dtsi-v1-0-d0ea9afdc007@quicinc.com> <20240904-qcs8300_initial_dtsi-v1-17-d0ea9afdc007@quicinc.com> <851566fe-4802-41c7-bb35-d6d1e9cf9bdf@kernel.org> Content-Language: en-US From: Jingyi Wang In-Reply-To: <851566fe-4802-41c7-bb35-d6d1e9cf9bdf@kernel.org> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 7bit X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01b.na.qualcomm.com (10.47.209.197) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: q647ivrs9ZRbZX7a4zPRg0m0tAgTa4Nh X-Proofpoint-ORIG-GUID: q647ivrs9ZRbZX7a4zPRg0m0tAgTa4Nh X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-05_04,2024-09-04_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 bulkscore=0 clxscore=1015 suspectscore=0 phishscore=0 impostorscore=0 priorityscore=1501 mlxscore=0 mlxlogscore=999 spamscore=0 lowpriorityscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2407110000 definitions=main-2409050033 On 9/4/2024 5:39 PM, Krzysztof Kozlowski wrote: > On 04/09/2024 10:33, Jingyi Wang wrote: >> Enable clock controller, interrconnect and pinctrl for QCS8300. > > NXP QCS8300? What is QCS8300? Which products use it? That's a defconfig > for entire kernel, not your Qualcomm one. > Will describe it in more detail. >> It needs to be built-in for UART to provide a console. >> >> Signed-off-by: Jingyi Wang >> --- >> arch/arm64/configs/defconfig | 3 +++ >> 1 file changed, 3 insertions(+) >> >> diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig >> index 81ca46e3ab4b..a9ba6b25a0ed 100644 >> --- a/arch/arm64/configs/defconfig >> +++ b/arch/arm64/configs/defconfig >> @@ -606,6 +606,7 @@ CONFIG_PINCTRL_MSM8996=y >> CONFIG_PINCTRL_MSM8998=y >> CONFIG_PINCTRL_QCM2290=y >> CONFIG_PINCTRL_QCS404=y >> +CONFIG_PINCTRL_QCS8300=y >> CONFIG_PINCTRL_QDF2XXX=y >> CONFIG_PINCTRL_QDU1000=y >> CONFIG_PINCTRL_SA8775P=y >> @@ -1317,6 +1318,7 @@ CONFIG_MSM_MMCC_8998=m >> CONFIG_QCM_GCC_2290=y >> CONFIG_QCM_DISPCC_2290=m >> CONFIG_QCS_GCC_404=y >> +CONFIG_QCS_GCC_8300=y >> CONFIG_QDU_GCC_1000=y >> CONFIG_SC_CAMCC_8280XP=m >> CONFIG_SC_DISPCC_7280=m >> @@ -1618,6 +1620,7 @@ CONFIG_INTERCONNECT_QCOM_MSM8996=y >> CONFIG_INTERCONNECT_QCOM_OSM_L3=m >> CONFIG_INTERCONNECT_QCOM_QCM2290=y >> CONFIG_INTERCONNECT_QCOM_QCS404=m >> +CONFIG_INTERCONNECT_QCOM_QCS8300=y > > Why this cannot be a module? > > I think the commit-msg "It needs to be built-in for UART to provide a console." can explain that, could you please help to share your insights on that? > > Best regards, > Krzysztof > Thanks, Jingyi