Re: [PATCH v3 0/4] phy: qcom-mipi-csi2: Add D-PHY support for sa8775p, qcs8300 and sc7280

[Anusha Arun Nandi <anusha.nandi@oss.qualcomm.com>]

Hi Krzysztof,

Sorry for missing the answers in v2. Here are the answers to questions
in v2.
1. Q:
https://lore.kernel.org/all/f319ba87-5569-4323-ae4c-3f9f34a9a3c1@kernel.org/#t
       v1 link is -
https://lore.kernel.org/all/20261016235502.2274268-1-anusha.nandi@oss.qualcomm.com/
      v2 link is -
https://lore.kernel.org/all/20261103214105.3605181-1-anusha.nandi@oss.qualcomm.com/
      In this v3. these comments have been addressed and updated
accordingly.

2. Q:
https://lore.kernel.org/all/a103b49e-e13f-4c70-b9a0-261534cfef79@kernel.org/
   That Reviewed-by was given in an internal review, not on a public
list thread.

3. Q:
https://lore.kernel.org/all/fe8bfa99-3fbb-4634-b99b-a36c2f8b35e5@kernel.org/
   Agreed on both points. Why it existed: it wasn't added on a guess
that some SoCs would need a different names. In v1
(https://lore.kernel.org/all/20261016235502.2274268-1-anusha.nandi@oss.qualcomm.com/),
timer_clk_name/opp_clk_name were added inline as part of the sa8775p
patch itself. Bryan asked only that it be split into its own standalone
patch ahead of the SoC
work(https://lore.kernel.org/all/392642ad-3bac-48bc-9199-8c3923c588c2@kernel.org/),
not that the configurability be justified or kept. I did the split for
v2 to verify whether the original premise still made sense. This driver
does not support platforms such as x1e80100, sa8775p, or sc7280, nor do
any of them ever declare a different clock name.
  Dropping the patch entirely in v3 rather than reworking it.
"timer"/"core" go back to being hardcoded literals, same as before v1
introduced the configurable fields.

4. Q:
https://lore.kernel.org/all/8942bbed-cd53-44a4-8559-c18fb2073bb2@kernel.org/
    Reviewed-by: given in an internal review, not on a public thread, no
lore link exists.
    On sc7280_clks[] and "what is the point of patch #2", the array
itself has a point: each SoC's soc_cfg needs its own two-entry clk_names
array matching its DT clock-names, same as x1e80100's and sa8775p's.
What had no point was patch #2 (dropped in v3) adding a second,
overridable name on top of that array, timer_clk_name/opp_clk_name, when
every one of those arrays already says, "core"/"timer" and nothing ever
varies it. In v3, sc7280_clks[] = {"core", "timer"} stands on its own,
unconditionally used, no override field anywhere.

Best regards,
Anusha
On 11/5/2026 3:51 PM, Anusha Arun Nandi wrote:
> This series extends the generic Qualcomm MIPI CSI2 PHY driver
> (drivers/phy/qualcomm/phy-qcom-mipi-csi2-*) with three additional
> CSIPHY variants: SA8775P, QCS8300 and SC7280. The driver currently
> only supports x1e80100; these SoCs let CAMSS consume the CSIPHY through
> the common PHY framework instead of the CSIPHY logic embedded in the
> legacy in-tree CAMSS driver.
> 
> QCS8300 shares the same CSIPHY D-PHY hardware as SA8775P, so it does
> not need its own of_device_id entry: the qcom,csi2-phy.yaml binding
> declares "qcom,sa8775p-csi2-phy" as QCS8300's fallback compatible, and
> QCS8300 CSIPHY nodes bind through patch 3's existing
> "qcom,sa8775p-csi2-phy" match entry.
> 
> Tested on sa8775p, qcs8300 and sc7280.
> 
> Changes in v3:
> - Patch 1 (binding): renamed vdda-phy-supply/vdda-pll-supply to
>   vdda-hs-supply/vdda-lp-supply, and restored the DPHY split-mode
>   port@0 definition (two endpoints, lane-count constraint) that was
>   dropped from the combined schema, cloning it from
>   qcom,x1e80100-csi2-phy.yaml instead.
> - Dropped "phy: qcom-mipi-csi2: Make timer and OPP clock names
>   configurable": no SoC this driver supports actually needs different
>   clock names, so the patch had no real effect.
> - Patch 2 ("Make OPP table optional") no longer depends on the
>   dropped patch's configurable opp_clk_name field; it now adds a
>   plain no_opp bool instead, with "timer"/"core" kept as hardcoded
>   literals.
> - Patches 3 and 4 (sa8775p, sc7280) dropped their now-unnecessary
>   timer_clk_name/opp_clk_name overrides, and renamed their
>   vdda-phy/vdda-pll supplies to vdda-hs/vdda-lp to match patch 1.
> 
> Link to v2: https://lore.kernel.org/all/20261103214105.3605181-1-anusha.nandi@oss.qualcomm.com/
> 
> Changes in v2:
> - Dropped "phy: qcom-mipi-csi2: fix -EEXIST probe failure on single
>   power-domain SoCs" from this series; posted standalone instead,
>   renamed to "Add support for single power-domain SoCs" since it adds
>   a case rather than fixing a bug.
> - Squashed the standalone qcom,sa8775p-csi2-phy.yaml/qcom,qcs8300 enum
>   addition/qcom,sc7280-csi2-phy.yaml schemas into one shared
>   qcom,csi2-phy.yaml, modelled as a oneOf compatible list instead of
>   one file per SoC.
> - Dropped the standalone "qcom,qcs8300-csi2-phy" of_device_id entry;
>   QCS8300 now binds through the sa8775p match entry via the binding's
>   fallback compatible instead, since the two SoCs are fully hardware
>   compatible.
> - Squashed the separate "Add qcs8300 CSI2 PHY support" patch into
>   "Add sa8775p D-PHY support" to match.
> 
> Link to v1: https://lore.kernel.org/all/20261016235502.2274268-1-anusha.nandi@oss.qualcomm.com/
> 
> Anusha Arun Nandi (4):
>   dt-bindings: phy: qcom: Add common qcom,csi2-phy
>   phy: qcom-mipi-csi2: Make OPP table optional
>   phy: qcom-mipi-csi2: Add sa8775p D-PHY support
>   phy: qcom-mipi-csi2: Add sc7280 D-PHY provider
> 
>  .../bindings/phy/qcom,csi2-phy.yaml           | 201 +++++++++++++++
>  .../qualcomm/phy-qcom-mipi-csi2-3ph-dphy.c    | 228 +++++++++++++++++-
>  .../phy/qualcomm/phy-qcom-mipi-csi2-core.c    |  74 +++---
>  drivers/phy/qualcomm/phy-qcom-mipi-csi2.h     |   5 +
>  4 files changed, 474 insertions(+), 34 deletions(-)
>  create mode 100644 Documentation/devicetree/bindings/phy/qcom,csi2-phy.yaml
>  
> Best regards,