Re: [PATCH] perf/x86/intel: Avoid PEBS_ENABLE MSR access in PMI

["Liang, Kan" <kan.liang@linux.intel.com>]

On 11/15/2019 1:33 PM, Andi Kleen wrote:
>> @@ -2620,6 +2624,15 @@ static int handle_pmi_common(struct pt_regs *regs,
>> u64 status)
>>                  handled++;
>>                  x86_pmu.drain_pebs(regs);
>>                  status &= x86_pmu.intel_ctrl | GLOBAL_STATUS_TRACE_TOPAPMI;
>> +
>> +               /*
>> +                * PMI may land after cpuc->enabled=0 in x86_pmu_disable()
>> and
>> +                * PMI throttle may be triggered for the PMI.
>> +                * For this rare case, intel_pmu_pebs_disable() will not
>> touch
>> +                * MSR_IA32_PEBS_ENABLE. Explicitly disable the PEBS here.
>> +                */
>> +               if (unlikely(!cpuc->enabled && !cpuc->pebs_enabled))
>> +                       wrmsrl(MSR_IA32_PEBS_ENABLE, 0);
> 
> How does the enable_all() code know to reenable it in this case?

For this case, we know that perf is disabling the PMU. The PMI handler 
will not restore PMU state when it's inactive. The enable_all() will not 
be called.

Thanks,
Kan