Re: [PATCH net-next v3 2/4] phylib: add reset after clk enable support

[Richard Leitner <richard.leitner@skidata.com>]

Hi Andrew,

On 12/05/2017 06:34 PM, Andrew Lunn wrote:
> On Tue, Dec 05, 2017 at 02:25:58PM +0100, Richard Leitner wrote:
>> From: Richard Leitner <richard.leitner@skidata.com>
>>
>> Some PHYs need the refclk to be a continuous clock. Therefore they don't
>> allow turning it off and on again during operation. Nonetheless such a
>> clock switching is performed by some ETH drivers (namely FEC [1]) for
>> power saving reasons. An example for an affected PHY is the
>> SMSC/Microchip LAN8720 in "REF_CLK In Mode".
>>
>> In order to provide a uniform method to overcome this problem this patch
>> adds a new phy_driver flag (PHY_RST_AFTER_CLK_EN) and corresponding
>> function phy_reset_after_clk_enable() to the phylib. These should be
>> used to trigger reset of the PHY after the refclk is switched on again.
>>
>> This patch depends on the "phylib: Add device reset GPIO support" patch
>> submitted by Geert Uytterhoeven/Sergei Shtylyov [2].
>>
>> [1] commit e8fcfcd5684a ("net: fec: optimize the clock management to save power")
>> [2] https://patchwork.kernel.org/patch/10090149/
>>
>> Signed-off-by: Richard Leitner <richard.leitner@skidata.com>
> 
> Hi Richard
> 
> Same comment about moving text below the ---

Ok. Thanks for your feedback and review.

> 
> Reviewed-by: Andrew Lunn <andrew@lunn.ch>
> 

regards;Richard.L

>      Andrew
>