From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1757884AbcIGQfT (ORCPT ); Wed, 7 Sep 2016 12:35:19 -0400 Received: from comal.ext.ti.com ([198.47.26.152]:50537 "EHLO comal.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754490AbcIGQfR (ORCPT ); Wed, 7 Sep 2016 12:35:17 -0400 Subject: Re: [PATCH 0/5] Use mmio-sram driver for Keystone MSMC RAM To: Santosh Shilimkar , Santosh Shilimkar References: <20160901225846.31058-1-s-anna@ti.com> <287b7e1d-1453-2832-515d-e7e51373a3bc@oracle.com> CC: Russell King , Rob Herring , , , , Tero Kristo , Murali Karicheri , Vitaly Andrianov From: Suman Anna Message-ID: Date: Wed, 7 Sep 2016 11:31:35 -0500 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:45.0) Gecko/20100101 Thunderbird/45.2.0 MIME-Version: 1.0 In-Reply-To: <287b7e1d-1453-2832-515d-e7e51373a3bc@oracle.com> Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 09/07/2016 11:25 AM, Santosh Shilimkar wrote: > On 9/7/2016 9:22 AM, Suman Anna wrote: >> Hi Santosh, >> >> On 09/07/2016 11:11 AM, Santosh Shilimkar wrote: >>> Hi Suman, >>> >>> On 9/1/2016 3:58 PM, Suman Anna wrote: >>>> Hi, >>>> >>>> The Keystone 2 family of SoCs have an on-chip RAM called the >>>> Multicore Shared Memory (MSM) RAM. This RAM is accessible through >>>> the Multicore Shared Memory Controller (MSMC). This series represents >>>> these on-chip RAMs as sram nodes so that the memory allocations >>>> can be managed by the in-kernel mmio-sram driver. >>>> >>>> The first 4 patches adds the basic SRAM nodes on each of the SoCs, >>>> and the last patch enables the generic on-chip SRAM driver for >>>> keystone defconfig. >>>> >>> The series looks good in general but I would like to understand >>> the users of this memory in kernel. Is that going to be posted >>> as a follow up patch ? Is the Power controller going to make >>> use of this SRAM for PM code ? >> >> Yes, the users will eventually follow. Power Controller code is not >> gonna be using this SRAM, it has its own RAM. This memory is gonna be >> split between various functional features like IPC, OPTEE integration, >> we already have the Boot Monitor code using this. We will have the >> memory split by either having static child nodes or drivers requesting >> the memory using gen_pool API. >> > OK. Its good to add the code at least with one active user of it. > Since this has to anyway wait for another merge window, please post the > users of it so that I can pull the combined patchset. Yeah, will do. The first user will mostly be the corresponding child nodes for the boot monitor. regards Suman