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Wed, 10 Jun 2026 01:03:44 -0500 Message-ID: Date: Wed, 10 Jun 2026 11:33:43 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 4/4] spi: cadence-qspi: Prevent SPI NAND continuous reads To: Miquel Raynal , Mark Brown , Richard Weinberger , "Vignesh Raghavendra" CC: Thomas Petazzoni , , , , Michael Walle , "Takahiro Kuwano" , Pratyush Yadav , Steam Lin , References: <20260326-winbond-v7-0-rc1-cadence-cont-read-v1-0-0d626e1dfb2b@bootlin.com> <20260326-winbond-v7-0-rc1-cadence-cont-read-v1-4-0d626e1dfb2b@bootlin.com> Content-Language: en-US From: Santhosh Kumar K In-Reply-To: <20260326-winbond-v7-0-rc1-cadence-cont-read-v1-4-0d626e1dfb2b@bootlin.com> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS3PEPF0000C37D:EE_|MW5PR10MB5851:EE_ X-MS-Office365-Filtering-Correlation-Id: cde0eae1-7848-4c22-dbc8-08dec6b61726 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|23010399003|36860700016|82310400026|1800799024|7416014|376014|6133799003|22082099003|18002099003|4143699003|56012099006; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: 4i6Xp4YsmOUsGpK5UukG23CkR24DnZalo3G0KDmu76tmzpxrcz2C3wXxn4FyVFve/ogtKYSfpKDlbmQHm2e8QGHo47WfOqyY6/3XLRe0EIjz1ki8YKb2s4+3t7XHrCglxggXH118rxKJ7wqX5i6Dq6y9Y1CCqHkrE/udG1PCt8qxHemhDZ265rku0K6RygdIAzefPSx7W8t/ZQ9Y6dVZUw0BNHyhYoaEFuVtJgzkaiiM0ZuyzjzaOZBzh41jz3VcyTGGhNmVXVcjA359Uj74/3Gq2rhn64ANs9nraJuBbFQix/8XIPzR3NvrC4afMTy3d0yBNrisFifdn8Quuu22FAmcNs46IWT+dfZrNt8V2XoY0a5IQHCoRMcF1HVmsft+YZmhB4Ywq/6IsTQSbmRJb89a6AbLtR/DSW08dMkNFhf7izLSXyP6/MjY2Ay/nk+9 X-OriginatorOrg: ti.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Jun 2026 06:04:10.6915 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: cde0eae1-7848-4c22-dbc8-08dec6b61726 X-MS-Exchange-CrossTenant-Id: e5b49634-450b-4709-8abb-1e2b19b982b7 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=e5b49634-450b-4709-8abb-1e2b19b982b7;Ip=[198.47.21.194];Helo=[flwvzet200.ext.ti.com] X-MS-Exchange-CrossTenant-AuthSource: DS3PEPF0000C37D.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW5PR10MB5851 Hello Mark and Miquel, On 26/03/26 22:17, Miquel Raynal wrote: > TI AM62Ax errata i2351, entitled "OSPI: Direct Access Controller (DAC) > does not support Continuous Read mode with NAND Flash", explains that > the CS can be deasserted almost at any time during a transfer (basically > there is an interconnect arbitration every 1023 byte). This is an > expected internal behaviour of the controller, but this leads to > spurious CS deasserts. These are totally forbidden during SPI NAND > continuous read transfers, because they indicate an end of transfer and > the continuous read is then stopped on the flash side. > > I initially tried to query the flash type and geometry to decide whether > to apply a spi message size limit (there is a spi helper for that) but > we cannot reliably get up to the MTD structure to discriminate if it is > a NOR or a NAND we are playing with (it is not relevant to limit SPI NOR > transfers, they are not affected). If we actually take this path, what > limitation shall we enforce? The errata mentions 1023B, this is super > low, less than a typical page size (about 2k or 4k, for most of them), > so this is not usable. On my side, I only observed this problem on a > 2-page read in octal DTR mode with more than 12 dummy cycles. The > writesize summed with the oobsize could be a relevant boundary, but it > is still quite arbitrary. Hence, I opted for implementing a controller > capability flag, which then is used to decide whether the SPI NAND > continuous read feature can be enabled. > > Signed-off-by: Miquel Raynal Just to confirm, has this patch not been picked up yet? Regards, Santhosh. > --- > I do not know if all flavours of this controller have the same > limitation, or whether it is integration specific. As I only found > mention of this errata for the AM62 processor, I opted for limiting the > flag to a single compatible. > --- > drivers/spi/spi-cadence-quadspi.c | 8 ++++++++ > 1 file changed, 8 insertions(+) > > diff --git a/drivers/spi/spi-cadence-quadspi.c b/drivers/spi/spi-cadence-quadspi.c > index 649ff55333f0..9f9b3013aa5d 100644 > --- a/drivers/spi/spi-cadence-quadspi.c > +++ b/drivers/spi/spi-cadence-quadspi.c > @@ -1740,6 +1740,12 @@ static const struct spi_controller_mem_caps cqspi_mem_caps = { > .per_op_freq = true, > }; > > +static const struct spi_controller_mem_caps cqspi_am654_mem_caps = { > + .dtr = true, > + .per_op_freq = true, > + .no_cs_assertion = true, > +}; > + > static int cqspi_setup_flash(struct cqspi_st *cqspi) > { > struct platform_device *pdev = cqspi->pdev; > @@ -1797,6 +1803,8 @@ static int cqspi_probe(struct platform_device *pdev) > host->mode_bits = SPI_RX_QUAD | SPI_RX_DUAL; > host->mem_ops = &cqspi_mem_ops; > host->mem_caps = &cqspi_mem_caps; > + if (of_device_is_compatible(pdev->dev.of_node, "ti,am654-ospi")) > + host->mem_caps = &cqspi_am654_mem_caps; > > cqspi = spi_controller_get_devdata(host); > if (of_device_is_compatible(pdev->dev.of_node, "starfive,jh7110-qspi")) >