Re: [PATCH v4 2/4] riscv: dts: fix the icicle's #pwm-cells

[<Conor.Dooley@microchip.com>]

On 08/07/2022 15:29, Conor Dooley wrote:
> \#pwm-cells for the Icicle kit's fabric PWM was incorrectly set to 2 &
> blindly overridden by the (out of tree) driver anyway. The core can
> support inverted operation, so update the entry to correctly report its
> capabilities.
> 
> Fixes: 72560c6559b8 ("riscv: dts: microchip: add fpga fabric section to icicle kit")
> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>

Gah, I messed this patch up... I'll resend.

> ---
>   .../dts/microchip/mpfs-icicle-kit-fabric.dtsi |   2 +-
>   .../dts/microchip/mpfs-tysom-m-fabric.dtsi    |  18 ++
>   .../riscv/boot/dts/microchip/mpfs-tysom-m.dts | 185 ++++++++++++++++++
>   3 files changed, 204 insertions(+), 1 deletion(-)
>   create mode 100644 arch/riscv/boot/dts/microchip/mpfs-tysom-m-fabric.dtsi
>   create mode 100644 arch/riscv/boot/dts/microchip/mpfs-tysom-m.dts
> 
> diff --git a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi
> index 0d28858b83f2..e09a13aef268 100644
> --- a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi
> +++ b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi
> @@ -8,7 +8,7 @@ core_pwm0: pwm@41000000 {
>   		compatible = "microchip,corepwm-rtl-v4";
>   		reg = <0x0 0x41000000 0x0 0xF0>;
>   		microchip,sync-update-mask = /bits/ 32 <0>;
> -		#pwm-cells = <2>;
> +		#pwm-cells = <3>;
>   		clocks = <&fabric_clk3>;
>   		status = "disabled";
>   	};
> diff --git a/arch/riscv/boot/dts/microchip/mpfs-tysom-m-fabric.dtsi b/arch/riscv/boot/dts/microchip/mpfs-tysom-m-fabric.dtsi
> new file mode 100644
> index 000000000000..98f642e83ad4
> --- /dev/null
> +++ b/arch/riscv/boot/dts/microchip/mpfs-tysom-m-fabric.dtsi
> @@ -0,0 +1,18 @@
> +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> +/* Copyright (c) 2022 Microchip Technology Inc */
> +
> +// #include "dt-bindings/mailbox/miv-ihc.h"
> +
> +/ {
> +	fabric_clk3: fabric-clk3 {
> +		compatible = "fixed-clock";
> +		#clock-cells = <0>;
> +		clock-frequency = <62500000>;
> +	};
> +
> +	fabric_clk1: fabric-clk1 {
> +		compatible = "fixed-clock";
> +		#clock-cells = <0>;
> +		clock-frequency = <125000000>;
> +	};
> +};
> diff --git a/arch/riscv/boot/dts/microchip/mpfs-tysom-m.dts b/arch/riscv/boot/dts/microchip/mpfs-tysom-m.dts
> new file mode 100644
> index 000000000000..0b664c591255
> --- /dev/null
> +++ b/arch/riscv/boot/dts/microchip/mpfs-tysom-m.dts
> @@ -0,0 +1,185 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Original all-in-one devicetree:
> + * Copyright (C) 2020-2022 - Aldec
> + * Rewritten to use includes:
> + * Copyright (C) 2022 - Conor Dooley <conor.dooley@microchip.com>
> + */
> +
> +/dts-v1/;
> +
> +#include "mpfs.dtsi"
> +#include "mpfs-tysom-m-fabric.dtsi"
> +
> +/* Clock frequency (in Hz) of the rtcclk */
> +#define MTIMER_FREQ		1000000
> +
> +/ {
> +	model = "Aldec TySOM-M-MPFS250T";
> +	compatible = "aldec,tysom-m-mpfs250t", "microchip,mpfs";
> +
> +	aliases {
> +		ethernet0 = &mac0;
> +		ethernet1 = &mac1;
> +		serial0 = &mmuart0;
> +		serial1 = &mmuart1;
> +		serial2 = &mmuart2;
> +		serial3 = &mmuart3;
> +		serial4 = &mmuart4;
> +		gpio0 = &gpio0;
> +		gpio1 = &gpio2;
> +	};
> +
> +	chosen {
> +		stdout-path = "serial1:115200n8";
> +	};
> +
> +	cpus {
> +		timebase-frequency = <MTIMER_FREQ>;
> +	};
> +
> +	ddrc_cache_lo: memory@80000000 {
> +		device_type = "memory";
> +		reg = <0x0 0x80000000 0x0 0x2e000000>;
> +		status = "okay";
> +	};
> +
> +	ddrc_cache_hi: memory@1000000000 {
> +		device_type = "memory";
> +		reg = <0x10 0x00000000 0x0 0x40000000>;
> +		status = "okay";
> +	};
> +
> +	soc {
> +	};
> +
> +	leds {
> +		compatible = "gpio-leds";
> +		status = "okay";
> +
> +		led0 {
> +			gpios = <&gpio1 23 1>;
> +			default-state = "on";
> +			linux,default-trigger = "heartbeat";
> +		};
> +	};
> +};
> +
> +&i2c0 {
> +	status = "okay";
> +};
> +
> +&i2c1 {
> +	status = "okay";
> +	ina219: ina219@45 {
> +		status = "okay";
> +		compatible = "ti,ina219";
> +		reg = <0x45>;
> +		shunt-resistor = <0x7d0>;
> +	};
> +};
> +
> +&gpio1 {
> +	interrupts = <27 28 29 30 31 32 33 47 35 36 37 38 39 40 41 42 43 44 45 46 34 48 49 50>;
> +	status = "okay";
> +};
> +
> +&mac0 {
> +	status = "okay";
> +	phy-mode = "gmii";
> +	phy-handle = <&phy0>;
> +
> +};
> +
> +&mac1 {
> +	status = "okay";
> +	phy-mode = "gmii";
> +	phy-handle = <&phy1>;
> +	phy1: ethernet-phy@1 {
> +		reg = <1>;
> +		ti,fifo-depth = <0x01>;
> +	};
> +	phy0: ethernet-phy@0 {
> +		reg = <0>;
> +		ti,fifo-depth = <0x01>;
> +	};
> +};
> +
> +&mbox {
> +	status = "okay";
> +};
> +
> +&mmc {
> +	max-frequency = <200000000>;
> +	cap-mmc-highspeed;
> +	cap-sd-highspeed;
> +	no-1-8-v;
> +	disable-wp;
> +	status = "okay";
> +};
> +
> +&mmuart1 {
> +	status = "okay";
> +};
> +
> +&mmuart2 {
> +	status = "okay";
> +};
> +
> +&mmuart3 {
> +	status = "okay";
> +};
> +
> +&mmuart4 {
> +	status = "okay";
> +};
> +
> +&refclk {
> +	clock-frequency = <125000000>;
> +};
> +
> +&rtc {
> +	status = "okay";
> +};
> +
> +&spi0 {
> +	status = "okay";
> +};
> +
> +&spi1 {
> +	status = "okay";
> +	pseFlash@0 {
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +		compatible = "n25q128a11", "jedec,spi-nor";
> +		status = "okay";
> +		reg = <0x0>;
> +		spi-max-frequency = <10000000>;
> +
> +		partition@test-0 { /* test purposes */
> +			label = "qspi-test-0";
> +			reg = <0x00000000 0x00800000>;
> +		};
> +		partition@test-1 { /* test purposes */
> +			label = "qspi-test-1";
> +			reg = <0x00800000 0x00800000>;
> +		};
> +		partition@test-2 { /* test purposes */
> +			label = "qspi-test-2";
> +			reg = <0x01000000 0x00800000>;
> +		};
> +		partition@test-3 { /* test purposes */
> +			label = "qspi-test-3";
> +			reg = <0x01800000 0x00800000>;
> +		};
> +	};
> +};
> +
> +&syscontroller {
> +	status = "okay";
> +};
> +
> +&usb {
> +	status = "okay";
> +	dr_mode = "host";
> +};