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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b8fc735e587sm262157066b.2.2026.02.16.07.38.16 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 16 Feb 2026 07:38:17 -0800 (PST) Message-ID: Date: Mon, 16 Feb 2026 16:38:15 +0100 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 5/6] clk: qcom: Add support for Global clock controller on Eliza To: Abel Vesa , Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Luca Weiss , Taniya Das , Taniya Das Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Dmitry Baryshkov References: <20260216-eliza-clocks-v3-0-8afc5a7e3a98@oss.qualcomm.com> <20260216-eliza-clocks-v3-5-8afc5a7e3a98@oss.qualcomm.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: <20260216-eliza-clocks-v3-5-8afc5a7e3a98@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-GUID: Xu4G87GdFPEFWMXLVHFTUG9H-KVNpRLR X-Proofpoint-ORIG-GUID: Xu4G87GdFPEFWMXLVHFTUG9H-KVNpRLR X-Authority-Analysis: v=2.4 cv=M8dA6iws c=1 sm=1 tr=0 ts=699339eb cx=c_pps a=HLyN3IcIa5EE8TELMZ618Q==:117 a=FpWmc02/iXfjRdCD7H54yg==:17 a=IkcTkHD0fZMA:10 a=HzLeVaNsDn8A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=Mpw57Om8IfrbqaoTuvik:22 a=GgsMoib0sEa3-_RKJdDe:22 a=EUspDBNiAAAA:8 a=KMfLPvBZmY1kkHWJjzAA:9 a=QEXdDO2ut3YA:10 a=bTQJ7kPSJx9SKPbeHEYW:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMjE2MDEzMiBTYWx0ZWRfX4d9GYUml6AvM cMm1Tk6zzNmG6sea5qFoYA8yFwCR5vAjbpCQaWTmvEc3S6SPGAu5kBy9TUJLssrAHp/vTcDe6Ri WLt0dNEU9tM+hUAXEMcfe+WwZHPC9R5/u8fCoSzOF9pYOW3qLUrZ3xXQLE/gEBNLMJSKB8949j0 cGdAkV+gkErctDzN6l/kupsk0dHGSdL+/srM0k84Wg4Bc+Ti07vbPv6ydo/mZ7bynrx7F2EOiOq BQ1dVWsG4kluFAyRbs/uz3E5EYlfamSmmWj589KWHwb7WGWSPeZWm7oUudShR4TN8/sUz9CaBDu oHnFgEOb8pmfdzcM13VAUO8KSUuEPrYdUiRT3NN7TDjjQSt1E5lpf7yIePlyPgaVl1XJALViAUU UCvp/qbXAWdcBYTZCjLAQkxWcwNZjDzsaZQ1s9K/+/k1MDpuCgVBqrJ1vtuk30NhYWuXhSsky2V /Yd7q8m6T1o6wbWSURw== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-02-16_04,2026-02-16_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 adultscore=0 suspectscore=0 bulkscore=0 impostorscore=0 clxscore=1015 phishscore=0 lowpriorityscore=0 priorityscore=1501 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2601150000 definitions=main-2602160132 On 2/16/26 2:43 PM, Abel Vesa wrote: > From: Taniya Das > > Add support for Global clock controller for Eliza Qualcomm SoC. > > Signed-off-by: Taniya Das > Reviewed-by: Dmitry Baryshkov > Signed-off-by: Abel Vesa > --- [...] > +static struct clk_regmap_mux gcc_pcie_0_pipe_clk_src = { This and a number of others should be struct clk_regmap_phy_mux instead, cross-check with kaanapali and remember to drop the then-unused parentmaps [...] > + [GCC_CAMERA_HF_CLK_EN_SLP_STG] = { 0x26018, 1 }, > + [GCC_CAMERA_SF_CLK_EN_SLP_STG] = { 0x26028, 1 }, > + [GCC_CAMERA_HF_CLK_EN_SEL_SLP_STG] = { 0x26018, 2 }, > + [GCC_CAMERA_SF_CLK_EN_SEL_SLP_STG] = { 0x26028, 2 }, So SEL_SLP_STG=0x1 allows setting SLP_STG to =0x1 to assert the ARES, otherwise if SEL_SLP_STG=0x0, it's controlled by the HW state machine I don't think modelling the prior one as a reset is valid, but I don't know what considerations we need to take wrt dis/allowing hw control here and what the consumer expectations are. Taniya, would you know? Konrad