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Wed, 10 Jul 2024 12:02:23 +0000 (UTC) Message-ID: Date: Wed, 10 Jul 2024 14:02:22 +0200 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 3/5] drm/mediatek: Support "Pre-multiplied" blending in OVL To: shawn.sung@mediatek.com, Chun-Kuang Hu , Philipp Zabel , David Airlie , Daniel Vetter , Matthias Brugger Cc: dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Hsiao Chien Sung , CK Hu References: <20240710-alpha-blending-v3-0-289c187f9c6f@mediatek.com> <20240710-alpha-blending-v3-3-289c187f9c6f@mediatek.com> From: AngeloGioacchino Del Regno Content-Language: en-US In-Reply-To: <20240710-alpha-blending-v3-3-289c187f9c6f@mediatek.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Il 10/07/24 10:52, Hsiao Chien Sung via B4 Relay ha scritto: > From: Hsiao Chien Sung > > Support "Pre-multiplied" alpha blending mode on in OVL. > Before this patch, only the "coverage" mode is supported. > > Signed-off-by: Hsiao Chien Sung > Reviewed-by: CK Hu > --- > drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 32 +++++++++++++++++++++++++------- > 1 file changed, 25 insertions(+), 7 deletions(-) > > diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c > index add671c38613..89b439dcf3a6 100644 > --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c > +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c > @@ -56,8 +56,12 @@ > #define GMC_THRESHOLD_HIGH ((1 << GMC_THRESHOLD_BITS) / 4) > #define GMC_THRESHOLD_LOW ((1 << GMC_THRESHOLD_BITS) / 8) > > +#define OVL_CON_CLRFMT_MAN BIT(23) > #define OVL_CON_BYTE_SWAP BIT(24) > -#define OVL_CON_MTX_YUV_TO_RGB (6 << 16) > + > +/* OVL_CON_RGB_SWAP works only if OVL_CON_CLRFMT_MAN is enabled */ > +#define OVL_CON_RGB_SWAP BIT(25) > + > #define OVL_CON_CLRFMT_RGB (1 << 12) > #define OVL_CON_CLRFMT_ARGB8888 (2 << 12) > #define OVL_CON_CLRFMT_RGBA8888 (3 << 12) > @@ -65,6 +69,11 @@ > #define OVL_CON_CLRFMT_BGRA8888 (OVL_CON_CLRFMT_ARGB8888 | OVL_CON_BYTE_SWAP) > #define OVL_CON_CLRFMT_UYVY (4 << 12) > #define OVL_CON_CLRFMT_YUYV (5 << 12) > +#define OVL_CON_MTX_YUV_TO_RGB (6 << 16) > +#define OVL_CON_CLRFMT_PARGB8888 ((3 << 12) | OVL_CON_CLRFMT_MAN) Shouldn't this be (OVL_CON_CLRFMT_RGBA8888 | OVL_CON_CLRFMT_MAN) ?? That's getting written to the same register, so I'd guess this is like that; but then, if it is like that, why is it PARGB888 and not PRGBA888?! Regards, Angelo