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Tue, 16 Sep 2025 07:28:07 -0700 (PDT) X-Google-Smtp-Source: AGHT+IFaRdyreAXTN3R4VZO/4YJ07pyOClNXcalPfMJAt0v6xilHbu5B83Umf7EFNgBl+2P0ENNgmA== X-Received: by 2002:a17:90b:4b02:b0:327:b2a1:2964 with SMTP id 98e67ed59e1d1-32de4edd5c0mr24271789a91.15.1758032886468; Tue, 16 Sep 2025 07:28:06 -0700 (PDT) Received: from [10.217.217.28] ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-b54a387cc21sm14557763a12.28.2025.09.16.07.27.58 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 16 Sep 2025 07:28:05 -0700 (PDT) Message-ID: Date: Tue, 16 Sep 2025 19:57:56 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH V7 0/5] Add support for QCOM SPMI PMIC5 Gen3 ADC To: Krzysztof Kozlowski Cc: jic23@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, agross@kernel.org, andersson@kernel.org, lumag@kernel.org, dmitry.baryshkov@oss.qualcomm.com, konradybcio@kernel.org, daniel.lezcano@linaro.org, sboyd@kernel.org, amitk@kernel.org, thara.gopinath@gmail.com, lee@kernel.org, rafael@kernel.org, subbaraman.narayanamurthy@oss.qualcomm.com, david.collins@oss.qualcomm.com, anjelique.melendez@oss.qualcomm.com, kamal.wadhwa@oss.qualcomm.com, rui.zhang@intel.com, lukasz.luba@arm.com, devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-iio@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, cros-qcom-dts-watchers@chromium.org, quic_kotarake@quicinc.com, neil.armstrong@linaro.org, stephan.gerhold@linaro.org References: <20250826083657.4005727-1-jishnu.prakash@oss.qualcomm.com> <20250829-imaginary-dove-of-music-afdb36@kuoka> Content-Language: en-US From: Jishnu Prakash In-Reply-To: <20250829-imaginary-dove-of-music-afdb36@kuoka> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Authority-Analysis: v=2.4 cv=eeo9f6EH c=1 sm=1 tr=0 ts=68c973f8 cx=c_pps a=RP+M6JBNLl+fLTcSJhASfg==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=yJojWOMRYYMA:10 a=VwQbUJbxAAAA:8 a=EUspDBNiAAAA:8 a=a0YOPMXbwBXd-ClgL4oA:9 a=QEXdDO2ut3YA:10 a=iS9zxrgQBfv6-_F4QbHw:22 X-Proofpoint-ORIG-GUID: zxteKuTKHhFCXHl5ry72mJNk6GODM9ZR X-Proofpoint-GUID: zxteKuTKHhFCXHl5ry72mJNk6GODM9ZR X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwOTEzMDAzNiBTYWx0ZWRfX4YRj0u14qA9h V8V4C/Mg1dGu/U6NuYyxwNqZ+/4t8O6SKsvhVmhIFHY8ADvE3gyP0XD9Nb9LuG+j+7xYXKFoodn 4RV8C6wi/zYnJgl2VGUl7/i4jB61g5+q+ADEpO4gHmYiLAU2JWjecShtIgmfWb6CIpqRibshkWT psd8Jjy5VtQ0IvaENi1X5BfJwXwvrQ1+LmyAZnJShRqVGKJD1nNJzYy0d7Aq5IMO7mPSPDfNIKt 8QmNc3qHtlgGVLkZtPD9BrlHrUx3AvQ7HarCxIus5VIAjtmgwT4AhDbkr4cPxRXHwB6Sbq/Objf 98W4+U8rdpAHKOjGREfvDwIqwl3zqdYFKFdXD6DK3TY0Ofyz6K3rrN8XLU++yMRUYj/j4uFzzlI a7XV4j/Q X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1117,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-09-16_02,2025-09-12_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 malwarescore=0 impostorscore=0 bulkscore=0 adultscore=0 priorityscore=1501 phishscore=0 spamscore=0 clxscore=1015 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2507300000 definitions=main-2509130036 Hi Krzysztof, On 8/29/2025 12:41 PM, Krzysztof Kozlowski wrote: > On Tue, Aug 26, 2025 at 02:06:52PM +0530, Jishnu Prakash wrote: >> PMIC5 Gen3 has a similar ADC architecture to that on PMIC5 Gen2, >> with all SW communication to ADC going through PMK8550 which >> communicates with other PMICs through PBS. The major difference is >> that the register interface used here is that of an SDAM present on >> PMK8550, rather than a dedicated ADC peripheral. There may be more than one >> SDAM used for ADC5 Gen3. Each ADC SDAM has eight channels, each of which may >> be used for either immediate reads (same functionality as previous PMIC5 and >> PMIC5 Gen2 ADC peripherals) or recurring measurements (same as PMIC5 and PMIC5 >> Gen2 ADC_TM functionality). In this case, we have VADC and ADC_TM functionality >> combined into the same driver. >> >> Patch 1 is a cleanup, to move the QCOM ADC dt-bindings files from >> dt-bindings/iio to dt-bindings/iio/adc folder, as they are >> specifically for ADC devices. It also fixes all compilation errors >> with this change in driver and devicetree files and similar errors >> in documentation for dtbinding check. >> >> Patch 2 splits out the common ADC channel properties used on older >> VADC devices, which would also be reused on ADC5 Gen3. >> >> Patch 3 adds bindings for ADC5 Gen3 peripheral. >> >> Patch 4 adds the main driver for ADC5 Gen3. >> >> Patch 5 adds the auxiliary thermal driver which supports the ADC_TM >> functionality of ADC5 Gen3. >> >> Changes since v6: >> - Updated auxiliary device cleanup handling to fix memory freeing issues >> - Updated copyright license in newly added files > > Eveyrthing is an update.... What did you change in copyright and > license? And why? I replaced the 2025 copyright with the new yearless one in newly added files, following our new internal guidelines. There was no change in the license, I'll fix this line. > >> - Addressed some reviewer comments in documentation and driver patches. > > What changed specifically? I'll update the changelog here and in other patches to list all the changes clearly when pushing the next patch series. Thanks, Jishnu > >> - Link to v6: https://lore.kernel.org/all/20250509110959.3384306-1-jishnu.prakash@oss.qualcomm.com/ >> > > Best regards, > Krzysztof >