From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 451BCC433FE for ; Fri, 11 Nov 2022 15:19:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234133AbiKKPTd (ORCPT ); Fri, 11 Nov 2022 10:19:33 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42568 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234446AbiKKPTE (ORCPT ); Fri, 11 Nov 2022 10:19:04 -0500 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 29D958291C; Fri, 11 Nov 2022 07:18:19 -0800 (PST) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id E15CD1FB; Fri, 11 Nov 2022 07:18:24 -0800 (PST) Received: from [10.1.196.40] (e121345-lin.cambridge.arm.com [10.1.196.40]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 546EA3F73D; Fri, 11 Nov 2022 07:18:16 -0800 (PST) Message-ID: Date: Fri, 11 Nov 2022 15:18:10 +0000 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux aarch64; rv:102.0) Gecko/20100101 Thunderbird/102.2.2 Subject: Re: [PATCH v2 3/8] iommu/arm-smmu: Add definition for ARM_SMMU_CB_FSRRESTORE Content-Language: en-GB To: AngeloGioacchino Del Regno , agross@kernel.org Cc: andersson@kernel.org, konrad.dybcio@linaro.org, joro@8bytes.org, will@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, robdclark@gmail.com, linux-arm-msm@vger.kernel.org, iommu@lists.linux.dev, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, marijn.suijten@somainline.org, kernel@collabora.com, luca@z3ntu.xyz, a39.skl@gmail.com, phone-devel@vger.kernel.org, ~postmarketos/upstreaming@lists.sr.ht References: <20221111145919.221159-1-angelogioacchino.delregno@collabora.com> <20221111145919.221159-4-angelogioacchino.delregno@collabora.com> From: Robin Murphy In-Reply-To: <20221111145919.221159-4-angelogioacchino.delregno@collabora.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 11/11/2022 2:59 pm, AngeloGioacchino Del Regno wrote: > In preparation for adding a proper context bank reset sequence in > qcom_iommu, add a definition for the implementation defined Fault > Status Restore register (FSRRESTORE). It's not implementation defined, it's architectural. But I don't follow why we should need this. If we're resetting FSR, we don't need to restore any previous value to it; all we want to do is clear it, which we do already via its own mechanism. Thanks, Robin. > Signed-off-by: AngeloGioacchino Del Regno > --- > drivers/iommu/arm/arm-smmu/arm-smmu.h | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu.h b/drivers/iommu/arm/arm-smmu/arm-smmu.h > index 703fd5817ec1..5015138799c5 100644 > --- a/drivers/iommu/arm/arm-smmu/arm-smmu.h > +++ b/drivers/iommu/arm/arm-smmu/arm-smmu.h > @@ -219,6 +219,7 @@ enum arm_smmu_cbar_type { > ARM_SMMU_FSR_TF | \ > ARM_SMMU_FSR_IGN) > > +#define ARM_SMMU_CB_FSRRESTORE 0x5c > #define ARM_SMMU_CB_FAR 0x60 > > #define ARM_SMMU_CB_FSYNR0 0x68