From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from relay4-d.mail.gandi.net (relay4-d.mail.gandi.net [217.70.183.196]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 75AD5364A9 for ; Wed, 10 Jan 2024 06:48:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=ghiti.fr Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ghiti.fr Received: by mail.gandi.net (Postfix) with ESMTPSA id 3D475E0003; Wed, 10 Jan 2024 06:47:48 +0000 (UTC) Message-ID: Date: Wed, 10 Jan 2024 07:47:48 +0100 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH] RISC-V: only flush icache when it has VM_EXEC set Content-Language: en-US To: Yangyu Chen , linux-riscv@lists.infradead.org Cc: linux-kernel@vger.kernel.org, Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Conor Dooley , Jisheng Zhang , Andrew Waterman References: From: Alexandre Ghiti In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-GND-Sasl: alex@ghiti.fr Hi Yangyu, On 09/01/2024 19:48, Yangyu Chen wrote: > As I-Cache flush on current RISC-V needs to send IPIs to every CPU cores > in the system is very costly, limiting flush_icache_mm to be called only > when vma->vm_flags has VM_EXEC can help minimize the frequency of these > operations. It improves performance and reduces disturbances when Which platform did you test this patchset? Do you have any measurement of the performance improvements? > copy_from_user_page is needed such as profiling with perf. > > For I-D coherence concerns, it will not fail if such a page adds VM_EXEC > flags in the future since we have checked it in the __set_pte_at function. > > Signed-off-by: Yangyu Chen > --- > arch/riscv/include/asm/cacheflush.h | 7 +++++-- > 1 file changed, 5 insertions(+), 2 deletions(-) > > diff --git a/arch/riscv/include/asm/cacheflush.h b/arch/riscv/include/asm/cacheflush.h > index 3cb53c4df27c..915f532dc336 100644 > --- a/arch/riscv/include/asm/cacheflush.h > +++ b/arch/riscv/include/asm/cacheflush.h > @@ -33,8 +33,11 @@ static inline void flush_dcache_page(struct page *page) > * so instead we just flush the whole thing. > */ > #define flush_icache_range(start, end) flush_icache_all() > -#define flush_icache_user_page(vma, pg, addr, len) \ > - flush_icache_mm(vma->vm_mm, 0) > +#define flush_icache_user_page(vma, pg, addr, len) \ > +do { \ > + if (vma->vm_flags & VM_EXEC) \ > + flush_icache_mm(vma->vm_mm, 0); \ > +} while (0) > > #ifdef CONFIG_64BIT > #define flush_cache_vmap(start, end) flush_tlb_kernel_range(start, end) Otherwise, it looks good to me, so you can add: Reviewed-by: Alexandre Ghiti Thanks, Alex