From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3E093C433EF for ; Thu, 12 May 2022 15:32:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1355959AbiELPcT (ORCPT ); Thu, 12 May 2022 11:32:19 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56780 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1355646AbiELPcR (ORCPT ); Thu, 12 May 2022 11:32:17 -0400 Received: from frasgout.his.huawei.com (frasgout.his.huawei.com [185.176.79.56]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3A36420F758; Thu, 12 May 2022 08:32:15 -0700 (PDT) Received: from fraeml712-chm.china.huawei.com (unknown [172.18.147.226]) by frasgout.his.huawei.com (SkyGuard) with ESMTP id 4KzbKp6Spvz67ycC; Thu, 12 May 2022 23:29:18 +0800 (CST) Received: from lhreml724-chm.china.huawei.com (10.201.108.75) by fraeml712-chm.china.huawei.com (10.206.15.61) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.24; Thu, 12 May 2022 17:32:13 +0200 Received: from [10.47.25.226] (10.47.25.226) by lhreml724-chm.china.huawei.com (10.201.108.75) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.24; Thu, 12 May 2022 16:32:11 +0100 Message-ID: Date: Thu, 12 May 2022 16:32:09 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:91.0) Gecko/20100101 Thunderbird/91.6.1 Subject: Re: [PATCH 01/20] perf vendors events arm64: Arm Cortex-A5 To: Nick Forrington , , , CC: Will Deacon , Mathieu Poirier , Leo Yan , Peter Zijlstra , Ingo Molnar , Mark Rutland , Alexander Shishkin , Jiri Olsa , "Namhyung Kim" , Andi Kleen , Kajol Jain , James Clark , Andrew Kilroy References: <20220510104758.64677-1-nick.forrington@arm.com> <20220510104758.64677-2-nick.forrington@arm.com> From: John Garry In-Reply-To: <20220510104758.64677-2-nick.forrington@arm.com> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-Originating-IP: [10.47.25.226] X-ClientProxiedBy: lhreml748-chm.china.huawei.com (10.201.108.198) To lhreml724-chm.china.huawei.com (10.201.108.75) X-CFilter-Loop: Reflected Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 10/05/2022 11:47, Nick Forrington wrote: > --- a/tools/perf/pmu-events/arch/arm64/common-and-microarch.json > +++ b/tools/perf/pmu-events/arch/arm64/common-and-microarch.json > @@ -35,6 +35,18 @@ > "EventName": "L1D_TLB_REFILL", > "BriefDescription": "Attributable Level 1 data TLB refill" > }, This is a comment on the general situation of pmu-events support for arm64: > + { > + "PublicDescription": "Instruction architecturally executed, condition code check pass, load", > + "EventCode": "0x06", > + "EventName": "LD_RETIRED", > + "BriefDescription": "Instruction architecturally executed, condition code check pass, load" > + }, > + { > +[ > + { > + "ArchStdEvent": "L1I_CACHE_REFILL" > + }, The JSONs for some cores list these common arch events and some don't. The effect (if we do) is that the perf tool creates the alias for the event and we get all the event info in "perf list", which is useful. It would be good to have consistency here, but so many arm implementations exist and it's tricky to have all cores supported in pmu-events. So I had a patch series which makes perf read the armv8 pmu sysfs event file to learn all the events which the core supports and create the aliases from that. So, in this, we don't require the JSONs to list these events explicitly. Maybe I'll revisit it soon. Thanks, John