From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.1 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 532A1C04E87 for ; Tue, 21 May 2019 17:14:16 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 249F6217D7 for ; Tue, 21 May 2019 17:14:16 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=nvidia.com header.i=@nvidia.com header.b="At4Xdpw0" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728917AbfEUROP (ORCPT ); Tue, 21 May 2019 13:14:15 -0400 Received: from hqemgate16.nvidia.com ([216.228.121.65]:3463 "EHLO hqemgate16.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726900AbfEUROO (ORCPT ); Tue, 21 May 2019 13:14:14 -0400 Received: from hqpgpgate102.nvidia.com (Not Verified[216.228.121.13]) by hqemgate16.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Tue, 21 May 2019 10:14:12 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate102.nvidia.com (PGP Universal service); Tue, 21 May 2019 10:14:12 -0700 X-PGP-Universal: processed; by hqpgpgate102.nvidia.com on Tue, 21 May 2019 10:14:12 -0700 Received: from [10.25.72.115] (172.20.13.39) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Tue, 21 May 2019 17:14:06 +0000 Subject: Re: [PATCH V7 05/15] PCI: dwc: Add ext config space capability search API To: Thierry Reding CC: , , , , , , , , , , , , , , , , , , References: <20190517123846.3708-1-vidyas@nvidia.com> <20190517123846.3708-6-vidyas@nvidia.com> <20190521103629.GE29166@ulmo> X-Nvconfidentiality: public From: Vidya Sagar Message-ID: Date: Tue, 21 May 2019 22:44:04 +0530 User-Agent: Mozilla/5.0 (Windows NT 10.0; WOW64; rv:60.0) Gecko/20100101 Thunderbird/60.6.1 MIME-Version: 1.0 In-Reply-To: <20190521103629.GE29166@ulmo> X-Originating-IP: [172.20.13.39] X-ClientProxiedBy: HQMAIL103.nvidia.com (172.20.187.11) To HQMAIL107.nvidia.com (172.20.187.13) Content-Type: text/plain; charset="windows-1252"; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1558458852; bh=BcyBWuXsiZPLocS6gKpgICDF6NfMYJFTJoNUnlHyJbA=; h=X-PGP-Universal:Subject:To:CC:References:X-Nvconfidentiality:From: Message-ID:Date:User-Agent:MIME-Version:In-Reply-To: X-Originating-IP:X-ClientProxiedBy:Content-Type:Content-Language: Content-Transfer-Encoding; b=At4Xdpw0Zrn5NsJ2CRKYABUSOeeEfKMEt9N1cZC7IFh4aB1Xzp5/eiDTcuV0z5mjP +Rbrzd8Fajyae9wCzljeqfSzm5JLySCJAff9YBdPaLgv2ZH/aThQlJ/9cnr+rFQnbi zNiOaCci50OPFXQ1eukzFALbhyGokGYgBpkANGMkwOuYTK3SpNSszTSDZWWI4ri6oX +iCI/vHaoU+/DiFzRcflgqoK+oD4Fnik1RKZzbqptYuA+Keb4XnZ22V/s9bkkTGs8k 4TyGgUsgh/YnX95Pd9LfGJKmgUAfAZnW0LaisxnZ5WbcGLvIN0Tf0wMI53UXAIPeSK McpPwR6MFnj9Q== Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 5/21/2019 4:06 PM, Thierry Reding wrote: > On Fri, May 17, 2019 at 06:08:36PM +0530, Vidya Sagar wrote: >> Add extended configuration space capability search API using struct dw_pcie * >> pointer >> >> Signed-off-by: Vidya Sagar >> Acked-by: Gustavo Pimentel >> --- >> Changes since [v6]: >> * None >> >> Changes since [v5]: >> * None >> >> Changes since [v4]: >> * None >> >> Changes since [v3]: >> * None >> >> Changes since [v2]: >> * None >> >> Changes since [v1]: >> * This is a new patch in v2 series >> >> drivers/pci/controller/dwc/pcie-designware.c | 41 ++++++++++++++++++++ >> drivers/pci/controller/dwc/pcie-designware.h | 1 + >> 2 files changed, 42 insertions(+) >> >> diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c >> index 8f53ce63d17e..3b7d50888caa 100644 >> --- a/drivers/pci/controller/dwc/pcie-designware.c >> +++ b/drivers/pci/controller/dwc/pcie-designware.c >> @@ -54,6 +54,47 @@ u8 dw_pcie_find_capability(struct dw_pcie *pci, u8 cap) >> } >> EXPORT_SYMBOL_GPL(dw_pcie_find_capability); >> >> +static int dw_pcie_find_next_ext_capability(struct dw_pcie *pci, int start, >> + int cap) > > Perhaps make this more consistent with the existing regular > configuration space capability search API? Something like this perhaps: > > static u16 dw_pcie_find_next_ext_capability(struct dw_pcie *pci, > u16 start, u8 cap) > > ? I guess your variant above is consistent with the existing generic > capability search API, so another alternative might be to make the old > dw_pcie_find_capability() API consistent with everything else. It's > confusing if we keep having to jump between the two variants. Ok. I'll change it to the format being followed in this file i.e. using u16 and u8 > > Thierry > >> +{ >> + u32 header; >> + int ttl; >> + int pos = PCI_CFG_SPACE_SIZE; >> + >> + /* minimum 8 bytes per capability */ >> + ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8; >> + >> + if (start) >> + pos = start; >> + >> + header = dw_pcie_readl_dbi(pci, pos); >> + /* >> + * If we have no capabilities, this is indicated by cap ID, >> + * cap version and next pointer all being 0. >> + */ >> + if (header == 0) >> + return 0; >> + >> + while (ttl-- > 0) { >> + if (PCI_EXT_CAP_ID(header) == cap && pos != start) >> + return pos; >> + >> + pos = PCI_EXT_CAP_NEXT(header); >> + if (pos < PCI_CFG_SPACE_SIZE) >> + break; >> + >> + header = dw_pcie_readl_dbi(pci, pos); >> + } >> + >> + return 0; >> +} >> + >> +int dw_pcie_find_ext_capability(struct dw_pcie *pci, int cap) >> +{ >> + return dw_pcie_find_next_ext_capability(pci, 0, cap); >> +} >> +EXPORT_SYMBOL_GPL(dw_pcie_find_ext_capability); >> + >> int dw_pcie_read(void __iomem *addr, int size, u32 *val) >> { >> if (!IS_ALIGNED((uintptr_t)addr, size)) { >> diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h >> index 6cb978132469..fff284098117 100644 >> --- a/drivers/pci/controller/dwc/pcie-designware.h >> +++ b/drivers/pci/controller/dwc/pcie-designware.h >> @@ -252,6 +252,7 @@ struct dw_pcie { >> container_of((endpoint), struct dw_pcie, ep) >> >> u8 dw_pcie_find_capability(struct dw_pcie *pci, u8 cap); >> +int dw_pcie_find_ext_capability(struct dw_pcie *pci, int cap); >> >> int dw_pcie_read(void __iomem *addr, int size, u32 *val); >> int dw_pcie_write(void __iomem *addr, int size, u32 val); >> -- >> 2.17.1 >>