From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id EA9EB2D6409 for ; Tue, 21 Apr 2026 08:47:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776761279; cv=none; b=qloplkHTu1gjcdz95EbMif41JJmEG4R0sa8pFU9nNuVEeHA+rFAoVX4+hdjRE7AUa0Zv1GZ5JrNXINm1z+LdzeW0p0vJKpWuIgvVn+601idGDkF+/P6w1Pb1FkBNYJRO1llRoqjocfUrDpYX9XUNNki7W4PyTnpPfkhj+TTwQrA= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776761279; c=relaxed/simple; bh=tGHTJO3OLM2tPNvqAneG+wOR1j4TNZT+Lox+5bpZMnQ=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=lIPMW1ksiBKe3cfeGRNY0eURgGvaZC6vzxk7yoyjLkTGnVcybFJaceBDv1U+6W+vO7oTIYnmCX116OJlto5OA+p0QVcVXjCpZMzTa6RN/W1+6oFridm5QubEVWqhN7E6fjZiwRcfglPnyGKQfCVcyvQJi2z3RvstJQqkABHSW1o= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b=lDGs96Z4; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b="lDGs96Z4" Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 7FE1225E0; Tue, 21 Apr 2026 01:47:51 -0700 (PDT) Received: from [10.57.17.241] (unknown [10.57.17.241]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id A52A83F915; Tue, 21 Apr 2026 01:47:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1776761277; bh=tGHTJO3OLM2tPNvqAneG+wOR1j4TNZT+Lox+5bpZMnQ=; h=Date:Subject:To:Cc:References:From:In-Reply-To:From; b=lDGs96Z49uYUZQDLYjWkRtmQTDcjKBu2UzJIA66S9wjCdpk7SkTllYVQ2t1QQuFEy Z6MCQTey8RVl2MojuSsSN8z+8LbvxT8atmenhEA4bA7TIwxls7VYdgbt3fBNkP5nE+ 50Qr/0P2qI/0IOnjNqCBVob0sAFcdLFPcpCvSSkw= Message-ID: Date: Tue, 21 Apr 2026 09:47:54 +0100 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v5 01/12] coresight: etm4x: fix wrong check of etm4x_sspcicrn_present() Content-Language: en-GB To: Yeoreum Yun , coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: mike.leach@arm.com, james.clark@linaro.org, alexander.shishkin@linux.intel.com, leo.yan@arm.com, jie.gan@oss.qualcomm.com References: <20260415165528.3369607-1-yeoreum.yun@arm.com> <20260415165528.3369607-2-yeoreum.yun@arm.com> From: Suzuki K Poulose In-Reply-To: <20260415165528.3369607-2-yeoreum.yun@arm.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 15/04/2026 17:55, Yeoreum Yun wrote: > According to Embedded Trace Macrocell Architecture Specification > ETMv4.0 to ETM4.6 [0], TRCSSPCICR is present only if all of > the following are true: > > - TRCIDR4.NUMSSCC > n. > - TRCIDR4.NUMPC > 0b0000. > - TRCSSCSR.PC == 0b1. > > Comment for etm4x_sspcicrn_present() is align with the specification. > However, the check should use drvdata->nr_pe_cmp to check TRCIDR4.NUMPC > not nr_pe. > > Link: https://developer.arm.com/documentation/ihi0064/latest/ [0] Fixes: f6a18f354c58 ("coresight: etm4x: Handle access to TRCSSPCICRn") With that looks good to me Suzuki > Signed-off-by: Yeoreum Yun > --- > drivers/hwtracing/coresight/coresight-etm4x-core.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c > index d565a73f0042..74b7063d130e 100644 > --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c > +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c > @@ -89,7 +89,7 @@ static int etm4_probe_cpu(unsigned int cpu); > static bool etm4x_sspcicrn_present(struct etmv4_drvdata *drvdata, int n) > { > return (n < drvdata->nr_ss_cmp) && > - drvdata->nr_pe && > + drvdata->nr_pe_cmp && > (drvdata->config.ss_status[n] & TRCSSCSRn_PC); > } >