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Thu, 06 Nov 2025 03:42:07 -0800 (PST) X-Google-Smtp-Source: AGHT+IGA9TIB8orqE5oPIwoVJXvrc38Pb3yNWldPGYOvWIlv3ebdEia7DEdvxcYxMUiRoVSNBpxMMw== X-Received: by 2002:a17:902:d48e:b0:24b:25f:5f81 with SMTP id d9443c01a7336-2962ad16addmr101806835ad.17.1762429326694; Thu, 06 Nov 2025 03:42:06 -0800 (PST) Received: from [10.218.35.45] ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-29650c5fdb5sm26117435ad.44.2025.11.06.03.42.02 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 06 Nov 2025 03:42:06 -0800 (PST) Message-ID: Date: Thu, 6 Nov 2025 17:12:01 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH] PCI: qcom: Program correct T_POWER_ON value for L1.2 exit timing To: Manivannan Sadhasivam Cc: Bjorn Helgaas , Lorenzo Pieralisi , =?UTF-8?Q?Krzysztof_Wilczy=C5=84ski?= , Rob Herring , Bjorn Helgaas , linux-pci@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, mayank.rana@oss.qualcomm.com, quic_vbadigan@quicinc.com References: <20251104175657.GA1861670@bhelgaas> Content-Language: en-US From: Krishna Chaitanya Chundru In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-Authority-Analysis: v=2.4 cv=AYu83nXG c=1 sm=1 tr=0 ts=690c8990 cx=c_pps a=MTSHoo12Qbhz2p7MsH1ifg==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=6UeiqGixMTsA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=VwQbUJbxAAAA:8 a=EUspDBNiAAAA:8 a=lcPbnEz4b48S40dIIKQA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=GvdueXVYPmCkWapjIL-Q:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMTA2MDA5MiBTYWx0ZWRfX5ru53ICLCePI mwkJA5KsvIoz1qCOBOVdEBhdRV6BLgEQnIHE5dJzcMaxY+wuQrcZbsDNqdO026k8zWl7+DIYrpz bAvKbBCBhz1DvwzlMQkM7z1HQQo137k26lcKdjzzaZmwiPTuWfW1lzzr3keV+onSciuyzF2C6Ga CkaPUAK2rYrVLKgcyWyE1ZXV0qB5LZyAckbZmbptzKmj2UBVg8x3J8DnL1o1rggZ2wPAqHk8g1d zA632SbMRw/Ru5UfnbQxHtrCP9gqkiOyJzUI1tVvvAtHdZtjyktB4EZ9Ce2DbPQUOTSNmljlMp7 HzFOniSho8Gy+c+kdm8e34Y6mw4ZurTZwxewbjGL25QNvTf9Xk1MUxEZdxQJcaJHxZNsflzBUqR 7J8IsZskjWfP7XjjQmUGvZUF8d6MuQ== X-Proofpoint-ORIG-GUID: UBBGH1pWgmTkjzBFC4dwIreWGjZCXpgS X-Proofpoint-GUID: UBBGH1pWgmTkjzBFC4dwIreWGjZCXpgS X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-11-06_03,2025-11-06_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 adultscore=0 lowpriorityscore=0 suspectscore=0 malwarescore=0 clxscore=1015 spamscore=0 phishscore=0 priorityscore=1501 impostorscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2510240001 definitions=main-2511060092 On 11/6/2025 11:51 AM, Manivannan Sadhasivam wrote: > On Thu, Nov 06, 2025 at 10:30:44AM +0530, Krishna Chaitanya Chundru wrote: >> On 11/4/2025 11:26 PM, Bjorn Helgaas wrote: >>> On Tue, Nov 04, 2025 at 05:42:45PM +0530, Krishna Chaitanya Chundru wrote: >>>> The T_POWER_ON indicates the time (in μs) that a Port requires the port >>>> on the opposite side of Link to wait in L1.2.Exit after sampling CLKREQ# >>>> asserted before actively driving the interface. This value is used by >>>> the ASPM driver to compute the LTR_L1.2_THRESHOLD. >>>> >>>> Currently, the root port exposes a T_POWER_ON value of zero in the L1SS >>>> capability registers, leading to incorrect LTR_L1.2_THRESHOLD calculations. >>>> This can result in improper L1.2 exit behavior and can trigger AER's. >>>> >>>> To address this, program the T_POWER_ON value to 80us (scale = 1, >>>> value = 8) in the PCI_L1SS_CAP register during host initialization. This >>>> ensures that ASPM can take the root port's T_POWER_ON value into account >>>> while calculating the LTR_L1.2_THRESHOLD value. >>> I think the question is whether the value depends on the circuit >>> design of a particular platform (and should therefore come from DT), >>> or whether it depends solely on the qcom device. >> Yes it depends on design. >>> PCIe r7.0, sec 5.5.4, says: >>> >>> The T_POWER_ON and Common_Mode_Restore_Time fields must be >>> programmed to the appropriate values based on the components and AC >>> coupling capacitors used in the connection linking the two >>> components. The determination of these values is design >>> implementation specific. >>> >>> That suggests to me that maybe there should be devicetree properties >>> related to these. Obviously these would not be qcom-specific since >>> this is standard PCIe stuff. >> Yes Bjorn these are PCIe stuff only, I can go to Device tree route if we >> have different values for each target, as of now we are using this same >> value in all targets as recommended by our HW team. If there is at least one >> more target or one more vendor who needs to program this we can take >> devicetree property route. >> >> I am ok to go with devicetree way also if you insists. - Krishna Chaitanya. >> > Since this is a PCI generic value, using devicetree property makes sense to me. Raised devicetree change here [PATCH] schemas: pci: Document PCIe T_POWER_ON - Krishna Chaitanya. > - Mani >