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[130.180.211.218]) by smtp.googlemail.com with ESMTPSA id 5b1f17b1804b1-4398a64febasm75324215e9.1.2025.02.19.06.43.38 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 19 Feb 2025 06:43:38 -0800 (PST) Message-ID: Date: Wed, 19 Feb 2025 15:43:37 +0100 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 2/2] irqchip: clocksource: fix jcore-pit irq request To: Artur Rojek , Yoshinori Sato , Rich Felker , John Paul Adrian Glaubitz , Thomas Gleixner , Uros Bizjak Cc: Geert Uytterhoeven , "D . Jeff Dionne" , Rob Landley , linux-sh@vger.kernel.org, linux-kernel@vger.kernel.org References: <20250216175545.35079-1-contact@artur-rojek.eu> <20250216175545.35079-3-contact@artur-rojek.eu> Content-Language: en-US From: Daniel Lezcano In-Reply-To: <20250216175545.35079-3-contact@artur-rojek.eu> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit On 16/02/2025 18:55, Artur Rojek wrote: > The jcore-aic irqchip does not have separate interrupt numbers reserved > for cpu-local vs global interrupts. Instead, the task of selecting this > property is being delegated to the device drivers requesting the given > irq. > > This quirk has not been taken into account while migrating jcore-pit to > request_percpu_irq(), resulting in a failure to register PIT interrupts. > > Fix this behavior by making the following changes: > 1) Explicitly register irq_set_percpu_devid() in jcore-pit. > 2) Provide enable_percpu_irq()/disable_percpu_irq() calls in jcore-pit. > 3) Make jcore-aic pass the correct per-cpu cookie to the irq handler by > using handle_percpu_devid_irq() instead of handle_percpu_irq(). > > Fixes: 69a9dcbd2d65 ("clocksource/drivers/jcore: Use request_percpu_irq()") > > Signed-off-by: Artur Rojek > --- How this patch should be merged ? It is touching irqchip and clocksource at the same time. May I pick it in the clocksource tree ? -- Linaro.org │ Open source software for ARM SoCs Follow Linaro: Facebook | Twitter | Blog