From: David Lechner <dlechner@baylibre.com>
To: Andy Shevchenko <andriy.shevchenko@intel.com>
Cc: Jonathan Santos <Jonathan.Santos@analog.com>,
linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org,
nuno.sa@analog.com, michael.hennerich@analog.com,
broonie@kernel.org, jonath4nns@gmail.com,
marcelo.schmitt1@gmail.com, andy@kernel.org
Subject: Re: [PATCH 0/6] spi: add multi-CS and per-transfer lane mask support
Date: Tue, 14 Jul 2026 09:44:19 -0500 [thread overview]
Message-ID: <d7531ab3-aa0e-4d82-9c1f-5b0db571f099@baylibre.com> (raw)
In-Reply-To: <alZHM1UJ2JnAdikw@ashevche-desk.local>
On 7/14/26 9:26 AM, Andy Shevchenko wrote:
> On Tue, Jul 14, 2026 at 09:09:02AM -0500, David Lechner wrote:
>> On 7/14/26 3:57 AM, Andy Shevchenko wrote:
>>> On Tue, Jul 14, 2026 at 02:55:31AM -0300, Jonathan Santos wrote:
>>>> This series introduces two SPI subsystem features: per-transfer chipselect
>>>> masks and multi-CS device support. Together they address the multi-device
>>>> setup described in [1] and the limitation noted in [2], where no SPI
>>>> controller completely handles logical chip selects beyond the first one.
>>>>
>>>> The first part of the set addresses multi-CS support. Some SPI controllers
>>>> can assert multiple chip selects simultaneously, but the existing code
>>>> hardcoded CS index 0 in both spi_set_cs() and of_spi_parse_dt(),
>>>> preventing this from working.
>>>>
>>>> The second part addresses dynamic lane selection for STRIPE mode. In
>>>> SPI_MULTI_LANE_MODE_STRIPE, all available lanes are currently always
>>>> active. Some peripherals need to select a different subset of rx/tx lanes
>>>> per transfer. New fields are added to the spi_transfer struct to allow
>>>> drivers to specify which lanes to use for each transfer. The documentation
>>>> is also updated to describe this new behavior.
>>>
>>>> [1]: https://lore.kernel.org/linux-iio/af0EGv172ZMl%2F6N5@JSANTO12-L01.ad.analog.com/T/#t
>>>> [2]: https://lore.kernel.org/all/20250915183725.219473-1-jonas.gorski@gmail.com/
>>>
>>> Mark usually "merges" a series like this and cover letter goes as merge commit
>>> message. With that in mind, can we use Link tags for the above? Like
>>>
>>> Link: ... [1]
>>> Link: ... [2]
>
>> Beware, that would cause b4 to add the links to every patch in the series.
>
> Even in `b4 shazam` case? I thought it adds only a single Link per patch,
> and leaves the original Links as is. No?
Last I checked (which was a while ago), all tags in the cover letter get
applied to all patches in the series.
>
> Also this can be done with the blank line before real tags, would it make
> it behave differently?
>
Don't know.
next prev parent reply other threads:[~2026-07-14 14:44 UTC|newest]
Thread overview: 25+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-07-14 5:55 Jonathan Santos
2026-07-14 5:55 ` [PATCH 1/6] spi: support simultaneous assertion of multiple CS Jonathan Santos
2026-07-14 9:06 ` Andy Shevchenko
2026-07-14 9:08 ` Nuno Sá
2026-07-14 5:56 ` [PATCH 2/6] spi: add per-transfer CS mask Jonathan Santos
2026-07-14 9:12 ` Nuno Sá
2026-07-14 9:23 ` Andy Shevchenko
2026-07-14 5:56 ` [PATCH 3/6] spi: spi-engine-ex: Add support for multi-CS devices Jonathan Santos
2026-07-14 9:17 ` Andy Shevchenko
2026-07-14 5:56 ` [PATCH 4/6] spi: Documentation: multiple-data-lanes: describe rx and tx lane mask Jonathan Santos
2026-07-14 5:56 ` [PATCH 5/6] spi: add rx and tx lane mask to spi_transfer struct Jonathan Santos
2026-07-14 9:22 ` Nuno Sá
2026-07-14 9:26 ` Andy Shevchenko
2026-07-14 15:18 ` David Lechner
2026-07-15 10:23 ` Nuno Sá
2026-07-14 5:57 ` [PATCH 6/6] spi: axi-spi-engine: add support for dynamic multi-lane selection Jonathan Santos
2026-07-14 10:29 ` Nuno Sá
2026-07-14 8:57 ` [PATCH 0/6] spi: add multi-CS and per-transfer lane mask support Andy Shevchenko
2026-07-14 14:09 ` David Lechner
2026-07-14 14:26 ` Andy Shevchenko
2026-07-14 14:44 ` David Lechner [this message]
2026-07-14 10:29 ` Nuno Sá
2026-07-14 15:02 ` David Lechner
2026-07-16 16:50 ` Jonathan Santos
2026-07-20 23:10 ` David Lechner
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