From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from vps0.lunn.ch (vps0.lunn.ch [156.67.10.101]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 043E636D; Mon, 15 Sep 2025 22:00:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=156.67.10.101 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757973640; cv=none; b=cz//SSa37xk9ZTPbbuqcjDqji1ctesZWclfCBft6bH5yqpIPBt+mkjVDZSiraLIH6Q8A6+mjpCUQyWNm13ttKaZP1LBg9rHO68i8Q5STpcfsAx8xtPWx42c0WzPr5THu3gE1a2qhcaGZ8rj14wJTY9Cp44wmdEcvdbl/pqgMKso= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757973640; c=relaxed/simple; bh=F3ygx1XnJ0aZdXPNxPfZUVAlWymDtaNfcC9NQKmy9U4=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=hi+cWmtv2xvyR+cmCi7XLxTr+n0bpduPJCwzU/VOpIbqnxZimaUfRti5uZjDvoZHz9VbxGZGsgc9xRj1mcAoKXkjpnPflAjHUMLo6EkAv2Ww+gjE162c0pkHY4wa4DTtiF2jhcUFy1SqkIlA2mwfqYkTatZoTyK6ZoupABITIJA= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=lunn.ch; spf=pass smtp.mailfrom=lunn.ch; dkim=pass (1024-bit key) header.d=lunn.ch header.i=@lunn.ch header.b=r0+zydyp; arc=none smtp.client-ip=156.67.10.101 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=lunn.ch Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=lunn.ch Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=lunn.ch header.i=@lunn.ch header.b="r0+zydyp" DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lunn.ch; s=20171124; h=In-Reply-To:Content-Disposition:Content-Type:MIME-Version: References:Message-ID:Subject:Cc:To:From:Date:From:Sender:Reply-To:Subject: Date:Message-ID:To:Cc:MIME-Version:Content-Type:Content-Transfer-Encoding: Content-ID:Content-Description:Content-Disposition:In-Reply-To:References; bh=8z0EBcsd04kPxFgdwa+FQA4OvMZj0/Dz/kBOR+ssQSw=; b=r0+zydypdjMlbthRhc0mMesXij dM6h+gC9SDF6mIgxDOYrr/tj4X8u2dzC/KTIv4n8uFQszhFlxTPDN+fEKvxmtJf1d6/wV2vVtXBGK xMHSCyQ6GuuMdY55rUGoFIqhQXmnv0w3fTI6cSwKNN5+xVNdPVPkvYjiVD9ENn0f/dxg=; Received: from andrew by vps0.lunn.ch with local (Exim 4.94.2) (envelope-from ) id 1uyHF9-008U8k-6s; Tue, 16 Sep 2025 00:00:15 +0200 Date: Tue, 16 Sep 2025 00:00:15 +0200 From: Andrew Lunn To: Bastien Curutchet Cc: Woojung Huh , UNGLinuxDriver@microchip.com, Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Marek Vasut , Thomas Petazzoni , =?iso-8859-1?Q?Miqu=E8l?= Raynal , Pascal Eberhard , netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH net-next v2 3/3] net: dsa: microchip: Set SPI as bus interface during reset for KSZ8463 Message-ID: References: <20250912-ksz-strap-pins-v2-0-6d97270c6926@bootlin.com> <20250912-ksz-strap-pins-v2-3-6d97270c6926@bootlin.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20250912-ksz-strap-pins-v2-3-6d97270c6926@bootlin.com> On Fri, Sep 12, 2025 at 11:09:14AM +0200, Bastien Curutchet wrote: > At reset, the KSZ8463 uses a strap-based configuration to set SPI as > bus interface. SPI is the only bus supported by the driver. If the > required pull-ups/pull-downs are missing (by mistake or by design to > save power) the pins may float and the configuration can go wrong > preventing any communication with the switch. > > Introduce a ksz8463_configure_straps_spi() function called during the > device reset. It relies on the 'strap-rxd*-gpios' OF properties and the > 'reset' pinmux configuration to enforce SPI as bus interface. > > Signed-off-by: Bastien Curutchet (Schneider Electric) Thanks for updating the commit messages, it is now a lot clearer why this is needed. Reviewed-by: Andrew Lunn Andrew